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path: root/drivers/clk/imx/clk.h
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* clk: imx: gate4: Switch imx_clk_gate4_flags() to clk_hw based APIAnson Huang2020-01-121-2/+5
| | | | | | | | | | Switch the imx_clk_gate4_flags() function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: gate3: Switch to clk_hw based APIPeng Fan2019-12-231-2/+5
| | | | | | | | | | Switch the imx_clk_hw_gate3_flags function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: add hw API imx_clk_hw_mux2_flagsPeng Fan2019-12-231-0/+10
| | | | | | | | Introduce hw based API imx_clk_hw_mux2_flags, then we could convert i.MX8MN clk driver to use hw based APIs. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: add imx_unregister_hw_clocksPeng Fan2019-12-231-0/+1
| | | | | | | | | | There is a non hw API based imx_unregister_clocks to unregister clocks when of_clk_add_provider failed. Add a hw API based imx_unregister_hw_clocks when of_clk_add_hw_provider failed. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: clk-composite-8m: Switch to clk_hw based APIPeng Fan2019-12-231-7/+22
| | | | | | | | | | | Switch the imx8m_clk_hw_composite_flags function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: clk-pll14xx: Switch to clk_hw based APIPeng Fan2019-12-231-0/+7
| | | | | | | | | | Switch the imx_clk_pll14xx function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw basedAbel Vesa2019-12-111-1/+1
| | | | | | | | | Renaming the imx_clk_divider_gate register function to imx_clk_hw_divider_gate to be more obvious it is clk_hw based. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw basedAbel Vesa2019-12-111-1/+1
| | | | | | | | | Renaming the imx_clk_pfdv2 register function to imx_clk_hw_pfdv2 to be more obvious it is clk_hw based. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: Rename the imx_clk_pllv4 to imply it's clk_hw basedAbel Vesa2019-12-111-1/+1
| | | | | | | | | Renaming the imx_clk_pllv4 register function to imx_clk_hw_pllv4 to be more obvious it is clk_hw based. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: Rename sccg and frac pll register to suggest clk_hwAbel Vesa2019-12-111-2/+10
| | | | | | | | | | Renaming the imx_clk_frac_pll and imx_clk_sccg_pll register functions to imx_clk_hw_frac_pll, respectively imx_clk_hw_sccg_pll to be more obvious that they are clk_hw based. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: imx7ulp composite: Rename to show is clk_hw basedAbel Vesa2019-12-111-1/+1
| | | | | | | | | Renaming the imx7ulp_clk_composite register function to imx7ulp_clk_hw_composite to show it is clk_hw based. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: pllv2: Switch to clk_hw based APIAbel Vesa2019-12-111-1/+4
| | | | | | | | | | Switch the imx_clk_pllv2 register function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: pllv1: Switch to clk_hw based APIAbel Vesa2019-12-111-1/+4
| | | | | | | | | | Switch the imx_clk_pllv1 register function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: Replace all the clk based helpers with macrosAbel Vesa2019-12-111-27/+12
| | | | | | | | | | | | | | | | Replacing with macros all the clk based API helpers we reduce the code duplication. The end goal is to get rid of all these macros when there will be no more users of the clk based API, that is, when all the i.MX clock provider drivers will be switched completely to the clk_hw based API. This is another step in moving away from the non clk_hw based API usage throughout the i.MX clock drivers. The reason for doing that is to have a clear split between the clock provider and the clock consumer API. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: Rename the SCCG to SSCGAbel Vesa2019-12-111-2/+2
| | | | | | | | According to the manual the acronym stands for Spread Sprectum Clock Generator. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: Add correct failure handling for clk based helpersAbel Vesa2019-12-111-15/+22
| | | | | | | | | | | | | If the clk_hw based API returns an error, trying to return the clk from hw will end up in a NULL pointer dereference. So adding the to_clk checker and using it inside every clk based macro helper we handle that case correctly. This to_clk is also temporary and will go away along with the clk based macro helpers once there is no user that need them anymore. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHELeonard Crestez2019-12-091-0/+1
| | | | | | | | | | | | | | | | | DRAM frequency switches are executed in firmware and can change the configuration of the DRAM PLL outside linux. Mark these CLKs with CLK_GET_RATE_NOCACHE so we always read back the PLL config registers and recalculate rates. In current DRAM frequency tables on 8mm/8mn only the maximum frequency uses the PLL so it's always configured in the same way. However reading back the PLL configuration is the correct behavior and allows additional setpoints in the future. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx8mm: Move 1443X/1416X PLL clock structure to common placeAnson Huang2019-10-061-0/+3
| | | | | | | | | | | | | | | | Many i.MX8M SoCs use same 1443X/1416X PLL, such as i.MX8MM, i.MX8MN and later i.MX8M SoCs, moving these PLL definitions to pll14xx driver can save a lot of duplicated code on each platform. Meanwhile, no need to define PLL clock structure for every module which uses same type of PLL, e.g., audio/video/dram use 1443X PLL, arm/gpu/vpu/sys use 1416X PLL, define 2 PLL clock structure for each group is enough. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: Remove unused function statementAnson Huang2019-08-031-1/+0
| | | | | | | | | | imx_register_uart_clocks_hws() function is NOT implemented at all, remove it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: Remove unused clk based APIAbel Vesa2019-08-031-24/+0
| | | | | | | | | | | | | | | | | Now that the i.MX6 and i.MX7 clock drivers have been switched to clk_hw based, we can remove the clk based API that is not used by any i.MX clock driver. The following APIs are going away now: - imx_clk_busy_divider - imx_clk_busy_mux - imx_clk_fixup_divider - imx_clk_fixup_mux - imx_clk_mux_ldb - imx_clk_gate_dis_flags - imx_clk_gate_flags Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: Add API for clk unregister when driver probe failAnson Huang2019-08-031-0/+1
| | | | | | | | | For i.MX clock drivers probe fail case, clks should be unregistered in the return path, this patch adds a common API for i.MX clock drivers to unregister clocks when fail. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx8mm: Make 1416X/1443X PLL macro definitions common for usageAnson Huang2019-08-031-0/+17
| | | | | | | | | 1416X/1443X PLL are used on i.MX8MM and i.MX8MN and maybe other i.MX8M series SoC later, the macro definitions of these PLLs' initialization should be common for usage. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: Switch wrappers to clk_hw based APIAbel Vesa2019-06-071-26/+65
| | | | | | | | | | Switch all the wrappers to clk_hw based API and rename them to indicate that. Add macros for clk based legacy users. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: clk-fixup-mux: Switch to clk_hw based APIAbel Vesa2019-06-071-0/+3
| | | | | | | | | | | Switch the imx_clk_fixup_mux function to clk_hw based API, rename accordingly and add a macro for clk based legacy. a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: clk-fixup-div: Switch to clk_hw based APIAbel Vesa2019-06-071-2/+5
| | | | | | | | | | Switch the imx_clk_fixup_divider function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: clk-gate-exclusive: Switch to clk_hw based APIAbel Vesa2019-06-071-1/+4
| | | | | | | | | | Switch the imx_clk_gate_exclusive function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: clk-pfd: Switch to clk_hw based APIAbel Vesa2019-06-071-1/+4
| | | | | | | | | | Switch the imx_clk_pfd function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: clk-pllv3: Switch to clk_hw based APIAbel Vesa2019-06-071-1/+4
| | | | | | | | | | | Switch the imx_clk_hw_pllv3 function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: clk-gate2: Switch to clk_hw based APIAbel Vesa2019-06-071-1/+6
| | | | | | | | | | Switch the clk_register_gate2 function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: clk-cpu: Switch to clk_hw based APIAbel Vesa2019-06-071-1/+4
| | | | | | | | | | Switch the clk_cpu clock registering function to clk_hw based API and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: clk-busy: Switch to clk_hw based APIAbel Vesa2019-06-071-2/+9
| | | | | | | | | | | Switch all the clk_busy clock registering functions to clk_hw based API. Keep around some clk based wrappers to be used by older imx platforms. This allows us to move closer to a clear split of consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: Add imx_obtain_fixed_clock clk_hw based variantAbel Vesa2019-06-071-0/+3
| | | | | | | | | | In order to move to clk_hw based API, imx_obtain_fixed_clock_hw is added. The end goal here is to have all the clk providers use the clk_hw based API. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: Add common API for masking MMDC handshakeAnson Huang2019-05-231-0/+1
| | | | | | | | | | All i.MX6 SoCs need to mask unused MMDC channel's handshake for low power modes, this patch provides common API for masking the MMDC channel passed from caller. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: correct i.MX7D AV PLL num/denom offsetAnson Huang2019-04-291-0/+1
| | | | | | | | | | | According reference manual, i.MX7D's audio/video PLL's num/denom register offset are 0x20/0x30, they are different from i.MX6's audio/video PLL, correct it by introducing new offset variables for audio/video PLL and using runtime assignment based on PLL type. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: imx: Remove unused imx_get_clk_hw_fixedAbel Vesa2019-03-261-5/+0
| | | | | | | This is never used and the imx_clk_hw_fixed does the same thing. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: Refactor entire sccg pll clkAbel Vesa2019-02-261-3/+6
| | | | | | | | | | | | Make the entire combination of plls to be one single clock. The parents used for bypasses are specified each as an index in the parents list. The determine_rate does a lookup throughout all the possible combinations for all the divs and returns the best possible 'setup' which in turn is used by set_rate later to set up all the divs and bypasses. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Tested-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: imx: Add PLLs driver for imx8mm socBai Ping2019-02-211-0/+24
| | | | | | | | New PLLs are introduced on i.MX8M Mini SOC. PLL1416X is Integer PLL, PLL1443X is a Frac PLL. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: imx: Make parents const pointer in mux wrappersAbel Vesa2019-02-211-1/+2
| | | | | | | The parents needs to be pointer to const pointer to const char. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: imx: Make parent_names const pointer in composite-8mAbel Vesa2019-02-211-1/+1
| | | | | | | The parent_names needs to be pointer to const pointer to const char. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
*-. Merge branches 'clk-imx7ulp', 'clk-imx6-fixes', 'clk-imx-fixes', ↵Stephen Boyd2018-12-141-7/+153
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-imx8qxp' and 'clk-imx8mq' into clk-next - NXP i.MX7ULP SoC clock support - Support for i.MX8QXP SoC clocks - Support for NXP i.MX8MQ clock controllers * clk-imx7ulp: clk: imx: add imx7ulp clk driver clk: imx: implement new clk_hw based APIs clk: imx: make mux parent strings const dt-bindings: clock: add imx7ulp clock binding doc clk: imx: add imx7ulp composite clk support clk: imx: add pfdv2 support clk: imx: add pllv4 support clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support clk: imx: add gatable clock divider support * clk-imx6-fixes: clk: imx6q: handle ENET PLL bypass clk: imx6q: optionally get CCM inputs via standard clock handles clk: imx6q: reset exclusive gates on init * clk-imx-fixes: clk: imx6q: add DCICx clocks gate clk: imx6sl: ensure MMDC CH0 handshake is bypassed clk: imx7d: remove UART1 clock setting * clk-imx8qxp: clk: imx: add imx8qxp lpcg driver clk: imx: add lpcg clock support clk: imx: add imx8qxp clk driver clk: imx: add scu clock common part clk: imx: add configuration option for mmio clks dt-bindings: clock: add imx8qxp lpcg clock binding dt-bindings: clock: imx8qxp: add SCU clock IDs firmware: imx: add pm svc headfile dt-bindings: fsl: scu: update power domain binding firmware: imx: remove resource id enums dt-bindings: imx: add scu resource id headfile * clk-imx8mq: clk: imx: Make the i.MX8MQ CCM clock driver CLK_IMX8MQ dependant clk: imx: remove redundant initialization of ret to zero clk: imx: Add SCCG PLL type clk: imx: Add fractional PLL output clock clk: imx: Add clock driver for i.MX8MQ CCM clk: imx: Add imx composite clock dt-bindings: Add binding for i.MX8MQ CCM
| | * clk: imx: Add SCCG PLL typeLucas Stach2018-12-031-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SCCG is a new PLL type introduced on i.MX8. The description of this SCCG clock can be found here: https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834 Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: imx: Add fractional PLL output clockLucas Stach2018-12-031-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a new fractional clock type introduced on i.MX8. The description of this fractional clock can be found here: https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834 Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: imx: Add clock driver for i.MX8MQ CCMAbel Vesa2018-12-031-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver for the Clock Control Module found on i.MX8MQ. Signed-off-by: Anson Huang <anson.huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: imx: Add imx composite clockAbel Vesa2018-12-031-0/+16
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | Since a lot of clocks on imx8m are formed by a mux, gate, predivider and divider, the idea here is to combine all of those into one composite clock, but we need to deal with both predivider and divider at the same time and therefore we add the imx8m_clk_composite_divider_ops and register the composite clock with those. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Suggested-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: imx: implement new clk_hw based APIsA.s. Dong2018-12-031-0/+62
| | | | | | | | | | | | | | | | | | Clock providers are recommended to use the new struct clk_hw based API, so implement IMX clk_hw based provider helpers functions to the new approach. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: imx: make mux parent strings constA.s. Dong2018-12-031-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the commit 2893c379461a ("clk: make strings in parent name arrays const"), let's make the parent strings const, otherwise we may meet the following warning when compiling: drivers/clk/imx/clk-imx7ulp.c: In function 'imx7ulp_clocks_init': drivers/clk/imx/clk-imx7ulp.c:73:35: warning: passing argument 5 of 'imx_clk_mux_flags' discards 'const' qualifier from pointer target type clks[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_mux_flags("apll_pre_sel", base + 0x508, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); ^ In file included from drivers/clk/imx/clk-imx7ulp.c:23:0: drivers/clk/imx/clk.h:200:27: note: expected 'const char **' but argument is of type 'const char * const*' ... Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: imx: add imx7ulp composite clk supportA.s. Dong2018-12-031-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The imx composite clk is designed for Peripheral Clock Control (PCC) module observed in IMX ULP SoC series. NOTE pcc can only be operated when clk is gated. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Anson Huang <Anson.Huang@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@kernel.org: Include clk.h for sparse warnings] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: imx: add pfdv2 supportA.s. Dong2018-12-031-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP. NOTE pfdv2 can only be operated when clk is gated. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Anson Huang <Anson.Huang@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@kernel.org: Include clk.h for sparse warnings] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: imx: add pllv4 supportA.s. Dong2018-12-031-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pllv4 is designed for System Clock Generation (SCG) module observed in IMX ULP SoC series. e.g. i.MX7ULP. The SCG modules generates clock used to derive processor, system, peripheral bus and external memory interface clocks while this patch intends to support the PLL part. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Anson Huang <Anson.Huang@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@kernel.org: Include clk.h for sparse warnings] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: imx: add gatable clock divider supportA.s. Dong2018-12-031-0/+4
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For dividers with zero indicating clock is disabled, instead of giving a warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set" in exist code, we'd like to introduce enable/disable function for it. e.g. 000b - Clock disabled 001b - Divide by 1 010b - Divide by 2 ... Set rate when the clk is disabled will cache the rate request and only when the clk is enabled will the driver actually program the hardware to have the requested divider value. Similarly, when the clk is disabled we'll write a 0 there, but when the clk is enabled we'll restore whatever rate (divider) was chosen last. It does mean that recalc rate will be sort of odd, because when the clk is off it will return 0, and when the clk is on it will return the right rate. So to make things work, we'll need to return the cached rate in recalc rate when the clk is off and read the hardware when the clk is on. NOTE for the default off divider, the recalc rate will still return 0 as there's still no proper preset rate. Enable such divider will give user a reminder error message. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@kernel.org: Include clk.h for sparse warnings] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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