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path: root/drivers/clk/hisilicon/clk-hi3660.c
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* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152Thomas Gleixner2019-05-301-5/+1
* clk: hi3660: Mark clk_gate_ufs_subsys as criticalLeo Yan2019-04-191-1/+5
* clk: hi3660: fix incorrect uart3 clock freqencyZhong Kaihua2017-11-141-1/+1
* clk: hi3660: Set PPLL2 to 2880MZhong Kaihua2017-06-191-2/+2
* clk: hi3660: add clocks for video encoder, decoder and ISPChen Jun2017-06-191-0/+40
* clk: hi3660: fix wrong parent name of clk_mux_sysbusChen Jun2017-06-191-2/+4
* clk: Hi3660: register fixed_rate_clks with CLK_OF_DECLARE_DRIVERLeo Yan2017-06-191-10/+38
* clk: hisilicon: Add clock driver for hi3660 SoCZhangfei Gao2017-01-091-0/+567
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