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* xtensa: use "m" constraint instead of "a" in cmpxchg.h assemblyMax Filippov2019-11-261-15/+16
| | | | | | | | Use "m" constraint instead of "r" for the address, as "m" allows compiler to access adjacent locations using base + offset, while "r" requires updating the base register every time. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: use named assembly arguments in cmpxchg.hMax Filippov2019-11-261-35/+35
| | | | | | | | Numeric assembly arguments are hard to understand and assembly code that uses them is hard to modify. Use named arguments in __cmpxchg_u32 and xchg_u32. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: add exclusive atomics supportMax Filippov2019-05-071-2/+34
| | | | | | | | | Implement atomic primitives using exclusive access opcodes available in the recent xtensa cores. Since l32ex/s32ex don't have any memory ordering guarantees don't define __smp_mb__before_atomic/__smp_mb__after_atomic to make them use memw. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: provide xchg for sizes 1 and 2Max Filippov2019-02-071-4/+32
| | | | | | This is required for generic queued spinlocks, implement it. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: implement fake NMIMax Filippov2015-08-171-2/+2
| | | | | | | | | | | | | | | | In case perf IRQ is the highest of the medium-level IRQs, and is alone on its level, it may be treated as NMI: - LOCKLEVEL is defined to be one level less than EXCM level, - IRQ masking never lowers current IRQ level, - new fake exception cause code, EXCCAUSE_MAPPED_NMI is assigned to that IRQ; new second level exception handler, do_nmi, assigned to it handles it as NMI, - atomic operations in configurations without s32c1i still need to mask all interrupts. Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* arch: xtensa: include: asm: compiling issue, need cmpxchg64() defined.Chen Gang2013-06-051-0/+1
| | | | | | | | | | | | | When compiling with 'allmodconfig', some of drivers need cmpxchg64(), xtensa does not supply 64-bit implementation for 'xchg', so use the 'generic' implementation. e.g. (for next-20130527 tree): drivers/block/blockconsole.c:164:2: error: implicit declaration of function ‘cmpxchg64’ [-Werror=implicit-function-declaration] Signed-off-by: Chen Gang <gang.chen@asianux.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: clean up files to make them code-style compliantChris Zankel2012-12-181-1/+2
| | | | | | | Remove heading and trailing spaces, trim trailing lines, and wrap lines that are longer than 80 characters. Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: add s32c1i-based atomic ops implementationsMax Filippov2012-12-181-21/+50
| | | | | Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: reorganize SR referencingMax Filippov2012-10-151-2/+2
| | | | | | | | | | - reference SRs by names where possible, not by numbers; - get rid of __stringify around SR names where possible; - remove unneeded SR names from asm/regs.h; - add SREG_ prefix to remaining SR names; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* Disintegrate asm/system.h for XtensaDavid Howells2012-03-281-0/+131
Disintegrate asm/system.h for Xtensa. Signed-off-by: David Howells <dhowells@redhat.com> cc: Chris Zankel <chris@zankel.net>
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