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* riscv: clean up the macro format in each header fileZong Li2019-11-121-3/+3
| | | | | | | | | | There are many different formats in each header now, such as _ASM_XXX_H, __ASM_XXX_H, _ASM_RISCV_XXX_H, RISCV_XXX_H, etc., This patch tries to unify the format by using _ASM_RISCV_XXX_H, because the most header use it now. This patch also adds the conditional to the headers if they lost it. Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
* RISC-V: Add FP register ptrace support for gdb.Jim Wilson2018-10-221-0/+3
| | | | | | | | | | Add a variable and a macro to describe FP registers, assuming only D is supported. FP code is conditional on CONFIG_FPU. The FP regs and FCSR are copied separately to avoid copying struct padding. Tested by hand and with the gdb testsuite. Signed-off-by: Jim Wilson <jimw@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: Add definiion of extract symbol's index and type for 32-bitZong Li2018-07-041-2/+7
| | | | | | | Use generic marco to get the index and type of symbol. Signed-off-by: Zong Li <zong@andestech.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: Add definition of relocation typesZong Li2018-04-021-0/+7
| | | | | Signed-off-by: Zong Li <zong@andestech.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: User-facing APIPalmer Dabbelt2017-09-261-0/+83
This patch contains code that is in some way visible to the user: including via system calls, the VDSO, module loading and signal handling. It also contains some generic code that is ABI visible. Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
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