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path:
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/
arch
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mips
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kernel
/
smp-mt.c
Commit message (
Expand
)
Author
Age
Files
Lines
*
MIPS: Fix build error for non-malta VSMP kernel
Anoop P A
2012-08-22
1
-0
/
+2
*
Disintegrate asm/system.h for MIPS
David Howells
2012-03-28
1
-1
/
+0
*
atomic: use <linux/atomic.h>
Arun Sharma
2011-07-26
1
-1
/
+1
*
Fix common misspellings
Lucas De Marchi
2011-03-31
1
-1
/
+1
*
MIPS: MT: Fix typo in comment.
Ralf Baechle
2010-12-16
1
-1
/
+1
*
cpumask: Use accessors for cpu_*_mask: mips
Rusty Russell
2009-09-24
1
-1
/
+1
*
cpumask: arch_send_call_function_ipi_mask: mips
Rusty Russell
2009-09-24
1
-2
/
+2
*
cpumask: centralize cpu_online_map and cpu_possible_map
Rusty Russell
2008-12-13
1
-1
/
+1
*
[MIPS] Add support for MIPS CMP platform.
Ralf Baechle
2008-04-28
1
-81
/
+15
*
[MIPS] Remove TLB sanitation code
Chris Dearman
2008-04-28
1
-47
/
+0
*
[MIPS] SMP: Call platform methods via ops structure.
Ralf Baechle
2008-01-29
1
-87
/
+106
*
[MIPS] MT: Scheduler support for SMT
Ralf Baechle
2008-01-29
1
-1
/
+5
*
[MIPS] Fix "no space between function name and open parenthesis" warnings.
Ralf Baechle
2007-10-11
1
-1
/
+1
*
[MIPS] SMP: Scatter __cpuinit over the code as needed.
Ralf Baechle
2007-08-27
1
-3
/
+3
*
[MIPS] VSMP: Fix initialization ordering bug.
Ralf Baechle
2007-07-04
1
-2
/
+2
*
[MIPS] Separate performance counter interrupts
Chris Dearman
2007-06-14
1
-6
/
+6
*
[MIPS] Define MIPS_CPU_IRQ_BASE in generic header
Atsushi Nemoto
2007-02-06
1
-5
/
+4
*
[MIPS] use generic_handle_irq, handle_level_irq, handle_percpu_irq
Atsushi Nemoto
2006-11-30
1
-0
/
+2
*
[MIPS] VSMP: Synchronize cp0 counters on bootup.
Ralf Baechle
2006-10-31
1
-0
/
+2
*
[MIPS] VSMP: Fix initialization ordering bug.
Ralf Baechle
2006-10-31
1
-69
/
+83
*
[MIPS] Complete fixes after removal of pt_regs argument to int handlers.
Ralf Baechle
2006-10-08
1
-8
/
+8
*
[MIPS] MT: Initialise all writable bits in Cause register to zero.
Chris Dearman
2006-09-27
1
-1
/
+1
*
[PATCH] irq-flags: MIPS: Use the new IRQF_ constants
Thomas Gleixner
2006-07-02
1
-2
/
+2
*
[MIPS] FPU affinity for MT ASE.
Ralf Baechle
2006-04-19
1
-0
/
+11
*
[MIPS] MT: Improved multithreading support.
Ralf Baechle
2006-04-19
1
-0
/
+349