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* MIPS: Loongson 3: Add Loongson-3 SMP supportHuacai Chen2014-03-312-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IPI registers of Loongson-3 include IPI_SET, IPI_CLEAR, IPI_STATUS, IPI_EN and IPI_MAILBOX_BUF. Each bit of IPI_STATUS indicate a type of IPI and IPI_EN indicate whether the IPI is enabled. The sender write 1 to IPI_SET bits generate IPIs in IPI_STATUS, and receiver write 1 to bits of IPI_CLEAR to clear IPIs. IPI_MAILBOX_BUF are used to deliver more information about IPIs. Why we change code in arch/mips/loongson/common/setup.c? If without this change, when SMP configured, system cannot boot since it hang at printk() in cgroup_init_early(). The root cause is: console_trylock() \-->down_trylock(&console_sem) \-->raw_spin_unlock_irqrestore(&sem->lock, flags) \-->_raw_spin_unlock_irqrestore()(SMP/UP have different versions) \-->__raw_spin_unlock_irqrestore() (following is the SMP case) \-->do_raw_spin_unlock() \-->arch_spin_unlock() \-->nudge_writes() \-->mb() \-->wbflush() \-->__wbflush() In previous code __wbflush() is initialized in plat_mem_setup(), but cgroup_init_early() is called before plat_mem_setup(). Therefore, In this patch we make changes to avoid boot failure. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6638 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson: Add swiotlb to support All-Memory DMAHuacai Chen2014-03-312-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loongson doesn't support DMA address above 4GB traditionally. If memory is more than 4GB, CONFIG_SWIOTLB and ZONE_DMA32 should be selected. In this way, DMA pages are allocated below 4GB preferably. However, if low memory is not enough, high pages are allocated and swiotlb is used for bouncing. Moreover, we provide a platform-specific dma_map_ops::set_dma_mask() to set a device's dma_mask and coherent_dma_mask. We use these masks to distinguishes an allocated page can be used for DMA directly, or need swiotlb to bounce. Recently, we found that 32-bit DMA isn't a hardware bug, but a hardware configuration issue. So, latest firmware has enable the DMA support as high as 40-bit. To support all-memory DMA for all devices (besides the Loongson platform limit, there are still some devices have their own DMA32 limit), and also to be compatible with old firmware, we keep use swiotlb. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6636 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson 3: Add IRQ init and dispatch supportHuacai Chen2014-03-312-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IRQ routing path of Loongson-3: Devices(most) --> I8259 --> HT Controller --> IRQ Routing Table --> CPU ^ | Device(legacy devices such as UART) --> Bonito ---| IRQ Routing Table route 32 INTs to CPU's INT0~INT3(IP2~IP5 of CP0), 32 INTs include 16 HT INTs(mostly), 4 PCI INTs, 1 LPC INT, etc. IP6 is used for IPI and IP7 is used for internal MIPS timer. LOONGSON_INT_ROUTER_* are IRQ Routing Table registers. I8259 IRQs are 1:1 mapped to HT1 INTs. LOONGSON_HT1_* are configuration registers of HT1 controller. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6634 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson 3: Add HT-linked PCI supportHuacai Chen2014-03-312-0/+12
| | | | | | | | | | | | | | | | | | | | | | | Loongson family machines use Hyper-Transport bus for inter-core connection and device connection. The PCI bus is a subordinate linked at HT1. With LEFI firmware interface, We don't need fixup for PCI irq routing (except providing a VBIOS of the integrated GPU). Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6633 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson: Add UEFI-like firmware interface (LEFI) supportHuacai Chen2014-03-312-2/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new UEFI-like firmware interface (LEFI, i.e. Loongson Unified Firmware Interface) has 3 advantages: 1, Firmware export a physical memory map which is similar to X86's E820 map, so prom_init_memory() will be more elegant that #ifdef clauses can be removed. 2, Firmware export a pci irq routing table, we no longer need pci irq routing fixup in kernel's code. 3, Firmware has a built-in vga bios, and its address is exported, the linux kernel no longer need an embedded blob. With the LEFI interface, Loongson-3A/2G and all their successors can use a unified kernel. All Loongson-based machines support this new interface except 2E/2F series. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6632 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson 3: Add Lemote-3A machtypes definitionHuacai Chen2014-03-312-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | Add four Loongson-3 based machine types: MACH_LEMOTE_A1004/MACH_LEMOTE_A1201 are laptops; MACH_LEMOTE_A1101 is mini-itx; MACH_LEMOTE_A1205 is all-in-one machine. The most significant differrent between A1004/A1201 and A1101/A1205 is the laptops have EC but others don't. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6631 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson: Add basic Loongson-3 CPU supportHuacai Chen2014-03-311-0/+4
| | | | | | | | | | | | | | | | | | | Basic Loongson-3 CPU support include CPU probing and TLB/cache initializing. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6630 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson: Add basic Loongson-3 definitionHuacai Chen2014-03-314-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loongson-3 is a multi-core MIPS family CPU, it support MIPS64R2 fully. Loongson-3 has the same IMP field (0x6300) as Loongson-2. Loongson-3 has a hardware-maintained cache, system software doesn't need to maintain coherency. Loongson-3A is the first revision of Loongson-3, and it is the quad- core version of Loongson-2G. Loongson-3A has a simplified version named Loongson-2Gq, the main difference between Loongson-3A/2Gq is 3A has two HyperTransport controller but 2Gq has only one. HT0 is used for cross- chip interconnection and HT1 is used to link PCI bus. Therefore, 2Gq cannot support NUMA but 3A can. For software, Loongson-2Gq is simply identified as Loongson-3A. Exsisting Loongson family CPUs: Loongson-1: Loongson-1A, Loongson-1B, they are 32-bit MIPS CPUs. Loongson-2: Loongson-2E, Loongson-2F, Loongson-2G, they are 64-bit single-core MIPS CPUs. Loongson-3: Loongson-3A(including so-called Loongson-2Gq), they are 64-bit multi-core MIPS CPUs. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6629/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: MT: proc: Add support for printing VPE and TC idsRalf Baechle2014-03-311-0/+21
| | | | | | | | | | | | | | And there are more CPUs or configurations that want to provide special per-CPU information in /proc/cpuinfo. So I think there needs to be a hook mechanism, such as a notifier. This is a first cut only; I need to think about what sort of looking the notifier needs to have. But I'd appreciate testing on MT hardware! Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6066/
* MIPS: Loongson: Rename PRID_IMP_LOONGSON1 and PRID_IMP_LOONGSON2Huacai Chen2014-03-311-2/+2
| | | | | | | | | | | | | | | | | | | Loongson-1 is a 32-bit MIPS CPU and Loongson-2/3 are 64-bit MIPS CPUs, and both Loongson-2/3 has the same PRID IMP filed (0x6300). As a result, renaming PRID_IMP_LOONGSON1 and PRID_IMP_LOONGSON2 to PRID_IMP_LOONGSON_32 and PRID_IMP_LOONGSON_64 will make more sense. Signed-off-by: Huacai Chen <chenhc@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6552/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM47XX: Add Belkin F7Dxxxx board detectionCody P Schafer2014-03-261-0/+4
| | | | | | | | | | | | | | | Add a few Belkin F7Dxxxx entries, with F7D4401 sourced from online documentation and the "F7D7302" being observed. F7D3301, F7D3302, and F7D4302 are reasonable guesses which are unlikely to cause mis-detection. Signed-off-by: Cody P Schafer <devel@codyps.com> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Cc: zajec5@gmail.com Cc: Cody P Schafer <devel@codyps.com> Patchwork: https://patchwork.linux-mips.org/patch/6594/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM47XX: Add detection and GPIO config for Siemens SE505v2Hauke Mehrtens2014-03-261-0/+2
| | | | | | | | | | | | This adds board detection for the Siemens SE505v2 and the led gpio configuration. This board does not have any buttons. This is based on OpenWrt broadcom-diag and Manuel Munz's nvram dump. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Cc: zajec5@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/6593/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM47XX: Detect some more Linksys devicesHauke Mehrtens2014-03-261-1/+1
| | | | | | | | | | | | | | The Linksys WRT54G/GS/GL family uses the same boardtype numbers, and the same gpio configuration. The boardtype numbers are changing with the hardware versions, but these hardware numbers are different or each model. Detect them all as one device, this also worked in OpenWrt. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Cc: zajec5@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/6591/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add support for the M5150 processorLeonid Yegoshin2014-03-262-1/+2
| | | | | | | | | | | | | | The M5150 core is a 32-bit MIPS RISC which implements the MIPS Architecture Release-5 in a 5-stage pipeline. In addition, it includes the MIPS Architecture Virtualization Module that enables virtualization of operating systems, which provides a scalable, trusted, and secure execution environment. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6596/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add processor identifier for the M5150 processorLeonid Yegoshin2014-03-261-0/+1
| | | | | | | | Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6595/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: fold mach-db1xxx/db1x00 headers into board codeManuel Lauss2014-03-262-131/+0
| | | | | | | | | Merge the db1200.h and db1300.h headers into their only users. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/6660/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Extend DMA_MAYBE_COHERENT logic to DMA_NONCOHERENT useManuel Lauss2014-03-261-2/+2
| | | | | | | | | | Setting DMA_MAYBE_COHERENT gives a platform the opportunity to select use of cache ops at boot. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/6575/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: malta: Add support for SMP EVAMarkos Chandras2014-03-261-0/+6
| | | | | | | | Allow secondary cores to program their segment control registers during smp bootstrap code. This enables EVA on Malta SMP configurations Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: malta: malta-memory: Add support for the 'ememsize' variableMarkos Chandras2014-03-261-1/+1
| | | | | | | | | | | The 'ememsize' variable is used to denote the real RAM which is present on the Malta board. This is different compared to 'memsize' which is capped to 256MB. The 'ememsize' is used to get the actual physical memory when setting up the Malta memory layout. This only makes sense in case the core operates in the EVA mode, and it's ignored otherwise. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: malta: spaces.h: Add spaces.h file for Malta (EVA)Markos Chandras2014-03-261-0/+46
| | | | | | | Add a spaces.h file for Malta to override certain memory macros when operating in EVA mode. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: malta: Configure Segment Control registers for EVA bootMarkos Chandras2014-03-261-1/+108
| | | | | | | | | | | | | | | | | | | | | | The Malta board aliases 0x80000000 - 0xffffffff to 0x00000000 - 0x7fffffff ignoring the 256 MB IO hole in 0x10000000. The physical memory is shifted to 0x80000000 so up to 2GB can be used. Kuseg is expanded to 3GB (due to board limitations only 2GB can be accessed) and lowmem (kernel space) is expanded to 2GB. The Segment Control registers are programmed as follows: Virtual memory Physical memory Mapping 0x00000000 - 0x7fffffff 0x80000000 - 0xfffffffff MUSUK (kuseg) 0x80000000 - 0x9fffffff 0x00000000 - 0x1ffffffff MUSUK (kseg0) 0xa0000000 - 0xbf000000 0x00000000 - 0x1ffffffff MUSUK (kseg1) 0xc0000000 - 0xdfffffff - MK (kseg2) 0xe0000000 - 0xffffffff - MK (kseg3) The location of exception vectors remain the same since 0xbfc00000 (traditional exception base) still maps to 0x1fc00000 physical. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: mm: init: Add free_init_pages() callback for EVAMarkos Chandras2014-03-261-0/+2
| | | | | | | | A core in EVA mode can have any possible segment mapping, so the default free_initmem_default() function may not always work as expected. Therefore, add a callback that platforms can use to free up the init section. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: cpu: Add cpu flag for Enhanced Virtual AddressingMarkos Chandras2014-03-262-1/+4
| | | | | | | The MIPS *Aptiv family uses bit 28 in Config5 CP0 register to indicate whether the core supports EVA or not. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: page: Allow __pa_symbol overridesLeonid Yegoshin2014-03-261-0/+2
| | | | | | | | This will allow platforms to use an alternative way to get the physical address of a symbol. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: r4kcache: Add EVA cache flushing functionsLeonid Yegoshin2014-03-261-1/+151
| | | | | | | | | | Add EVA cache flushing functions similar to non-EVA configurations. Because the cache may or may not contain user virtual addresses, we need to use the 'cache' or 'cachee' instruction based on whether we flush the cache on behalf of kernel or user respectively. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: r4kcache: Add protected cache operation for EVALeonid Yegoshin2014-03-261-0/+18
| | | | | Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: r4kcache: Build flushing code for instruction cacheLeonid Yegoshin2014-03-261-0/+1
| | | | | | | | Build code to invalidate an address range in the instruction cache using the Hit Invalidate cache operation. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: checksum: Add MIPS specific csum_and_copy_from_user functionLeonid Yegoshin2014-03-261-0/+14
| | | | | | | | | | A MIPS specific csum_and_copy_from_user function is necessary because the generic one from include/net/checksum.h will not work for EVA. This is because the generic one will link to symbols from lib/checksum.c which are not EVA aware. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: checksum: Split kernel and user copy operationsLeonid Yegoshin2014-03-261-6/+16
| | | | | | | | | | In EVA mode, different instructions need to be used to read/write from kernel and userland. In non-EVA mode, there is no functional difference. The current address limit is checked to decide the type of operation that will be performed. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: checksum: Split the 'copy_user' symbolMarkos Chandras2014-03-261-6/+12
| | | | | | | | | | | | The 'copy_user' symbol can be used to copy from or to userland so we will use two different symbols for these operations. This makes no difference in the existing code, but when the core is operating in EVA mode, different instructions need to be used to read and write to userland address space. The old function has also been renamed to 'copy_kernel' to denote that it is suitable for copy data to and from kernel space. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: uaccess: Add EVA support for str*_user operationsMarkos Chandras2014-03-261-53/+119
| | | | | | | | | | | The str*_user functions are used to securely access NULL terminated strings from userland. Therefore, it's necessary to use the appropriate EVA function. However, if the string is in kernel space, then the normal instructions are being used to access it. The __str*_kernel_asm and __str*_user_asm symbols are the same for non-EVA mode so there is no functional change for the non-EVA kernels. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: uaccess: Add EVA support to copy_{in, to,from}_userMarkos Chandras2014-03-261-20/+171
| | | | | | | | | | | Use the EVA specific functions from memcpy.S to perform userspace operations. When get_fs() == get_ds() the usual load/store instructions are used because the destination address is located in the kernel address space region. Otherwise, the EVA specifc load/store instructions are used which will go through th TLB to perform the virtual to physical translation for the userspace address. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: uaccess: Rename {get,put}_user_asm macrosMarkos Chandras2014-03-261-30/+30
| | | | | | | | The {get,put}_user_asm functions can be used to load data from kernel or the user address space so rename them to avoid confusion. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: uaccess: Use EVA instructions wrappersMarkos Chandras2014-03-261-24/+109
| | | | | | | Use the EVA instruction wrappers from asm.h to perform read/write operations from userland. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: uaccess: Disable unaligned access macros for EVALeonid Yegoshin2014-03-261-0/+6
| | | | | | | | | | ulb, ulh, ulw are macros which emulate unaligned access for MIPS. However, no such macros exist for EVA mode, so the only way to do EVA unaligned accesses is in the ADE exception handler. As a result of which, disable these macros for EVA. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: uaccess: Move duplicated code to common functionMarkos Chandras2014-03-261-32/+29
| | | | | | | Similar to __get_user_* functions, move common code to __put_user_*_common so it can be shared among similar users. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: uaccess: Add instruction argument to __{put,get}_user_asmMarkos Chandras2014-03-261-13/+13
| | | | | | | | | In preparation for EVA support, an instruction argument is needed for the __get_user_asm{,_ll32} functions to allow instruction overrides in EVA mode. Even though EVA only works for MIPS 32-bit, both codepaths are changed (32-bit and 64-bit) for consistency reasons. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: uapi: inst: Add instruction format for SPECIAL3 instructionsLeonid Yegoshin2014-03-261-0/+11
| | | | | Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: uapi: inst: Add new EVA opcodesLeonid Yegoshin2014-03-261-4/+10
| | | | | Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: futex: Add EVA support for futex operationsMarkos Chandras2014-03-261-4/+5
| | | | | | | Use LLE/SCE instructions for performing an address translation for userspace when EVA is enabled. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: Add wrappers for EVA/non-EVA instructionsMarkos Chandras2014-03-262-0/+136
| | | | | | | | | EVA uses specific instructions for accessing user memory. Instead of polluting the kernel with numerous #ifdef CONFIG_EVA we add wrappers for all the instructions that need special handling when EVA is enabled. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: Add prefetch instruction for EVALeonid Yegoshin2014-03-261-0/+8
| | | | | | | | | EVA can use the PREFE instruction to perform the virtual address translation using the user mapping of the address rather than the kernel mapping. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Add cases for CPU_P5600James Hogan2014-03-261-0/+1
| | | | | | | | | | | Add a CPU_P5600 case to various switch statements, doing the same thing as for CPU_PROAPTIV. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6408/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add MIPS P5600 PRid and cputype identifiersJames Hogan2014-03-261-1/+2
| | | | | | | | | | Add a Processor ID and CPU type for the MIPS P5600 core. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6407/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Save/restore MSA context around signalsPaul Burton2014-03-262-0/+10
| | | | | | | | | | | | | | | This patch extends sigcontext in order to hold the most significant 64 bits of each vector register in addition to the MSA control & status register. The least significant 64 bits are already saved as the scalar FP context. This makes things a little awkward since the least & most significant 64 bits of each vector register are not contiguous in memory. Thus the copy_u & insert instructions are used to transfer the values of the most significant 64 bits via GP registers. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6533/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Basic MSA context switching supportPaul Burton2014-03-265-6/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Detect the MSA ASEPaul Burton2014-03-263-0/+8
| | | | | | | | | | | | | This patch adds support for probing the MSAP bit within the Config3 register in order to detect the presence of the MSA ASE. Presence of the ASE will be indicated in /proc/cpuinfo. The value of the MSA implementation register will be displayed at boot to aid debugging and verification of a correct setup, as is done for the FPU. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6430/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add MSA register definitions & accessPaul Burton2014-03-263-0/+297
| | | | | | | | | | | | | | | | | This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Don't assume 64-bit FP registers for context switchPaul Burton2014-03-262-128/+128
| | | | | | | | | | | | | | | | When saving or restoring scalar FP context we want to access the least significant 64 bits of each FP register. When the FP registers are 64 bits wide that is trivially the start of the registers value in memory. However when the FP registers are wider this equivalence will no longer be true for big endian systems. Define a new set of offset macros for the least significant 64 bits of each saved FP register within thread context, and make use of them when saving and restoring scalar FP context. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6428/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Update outdated commentPaul Burton2014-03-261-4/+3
| | | | | | | | | | | The hard-coded offsets mentioned in this comment seem to not exist anymore, so remove mention of them from the comment. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6421/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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