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| author | Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> | 2013-12-16 11:24:13 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-03-26 23:09:18 +0100 |
| commit | 41e62b0411d84e3d92deac79b83b0bacca4b9a52 (patch) | |
| tree | 563a98f0d83d77c4b3d414651646ef55c1cc9815 /arch/mips/include | |
| parent | ca750649e08ce37bd3873e1026dc245811adf7a8 (diff) | |
| download | talos-op-linux-41e62b0411d84e3d92deac79b83b0bacca4b9a52.tar.gz talos-op-linux-41e62b0411d84e3d92deac79b83b0bacca4b9a52.zip | |
MIPS: asm: r4kcache: Build flushing code for instruction cache
Build code to invalidate an address range in the instruction cache
using the Hit Invalidate cache operation.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/r4kcache.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h index c84caddb8bde..789792eeb4f1 100644 --- a/arch/mips/include/asm/r4kcache.h +++ b/arch/mips/include/asm/r4kcache.h @@ -456,6 +456,7 @@ __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, ) __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \ protected_, loongson2_) __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , ) +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , ) __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , ) /* blast_inv_dcache_range */ __BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , ) |
