diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-mips/cpu-features.h | 15 | ||||
| -rw-r--r-- | include/asm-mips/cpu.h | 40 | ||||
| -rw-r--r-- | include/asm-mips/mach-ip22/cpu-feature-overrides.h | 2 | ||||
| -rw-r--r-- | include/asm-mips/mach-mips/cpu-feature-overrides.h | 4 | ||||
| -rw-r--r-- | include/asm-mips/mach-rm200/cpu-feature-overrides.h | 2 | ||||
| -rw-r--r-- | include/asm-mips/mach-sim/cpu-feature-overrides.h | 4 |
6 files changed, 40 insertions, 27 deletions
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index 698c21125a5c..03627cfb3e45 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h @@ -25,8 +25,19 @@ #ifndef cpu_has_4kex #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) #endif -#ifndef cpu_has_4ktlb -#define cpu_has_4ktlb (cpu_data[0].options & MIPS_CPU_4KTLB) +#ifndef cpu_has_3k_cache +#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE) +#endif +#define cpu_has_6k_cache 0 +#define cpu_has_8k_cache 0 +#ifndef cpu_has_4k_cache +#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE) +#endif +#ifndef cpu_has_tx39_cache +#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) +#endif +#ifndef cpu_has_sb1_cache +#define cpu_has_sb1_cache (cpu_data[0].options & MIPS_CPU_SB1_CACHE) #endif #ifndef cpu_has_fpu #define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU) diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 2e8b5a48b99f..46b2a8dc2ee0 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -217,25 +217,27 @@ * CPU Option encodings */ #define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */ -/* Leave a spare bit for variant MMU types... */ -#define MIPS_CPU_4KEX 0x00000004 /* "R4K" exception model */ -#define MIPS_CPU_4KTLB 0x00000008 /* "R4K" TLB handler */ -#define MIPS_CPU_FPU 0x00000010 /* CPU has FPU */ -#define MIPS_CPU_32FPR 0x00000020 /* 32 dbl. prec. FP registers */ -#define MIPS_CPU_COUNTER 0x00000040 /* Cycle count/compare */ -#define MIPS_CPU_WATCH 0x00000080 /* watchpoint registers */ -#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */ -#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */ -#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */ -#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */ -#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */ -#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */ -#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */ -#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */ -#define MIPS_CPU_SUBSET_CACHES 0x00020000 /* P-cache subset enforced */ -#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */ -#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ -#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ +#define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */ +#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */ +#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */ +#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */ +#define MIPS_CPU_SB1_CACHE 0x00000020 /* SB1-style caches */ +#define MIPS_CPU_FPU 0x00000040 /* CPU has FPU */ +#define MIPS_CPU_32FPR 0x00000080 /* 32 dbl. prec. FP registers */ +#define MIPS_CPU_COUNTER 0x00000100 /* Cycle count/compare */ +#define MIPS_CPU_WATCH 0x00000200 /* watchpoint registers */ +#define MIPS_CPU_DIVEC 0x00000400 /* dedicated interrupt vector */ +#define MIPS_CPU_VCE 0x00000800 /* virt. coherence conflict possible */ +#define MIPS_CPU_CACHE_CDEX_P 0x00001000 /* Create_Dirty_Exclusive CACHE op */ +#define MIPS_CPU_CACHE_CDEX_S 0x00002000 /* ... same for seconary cache ... */ +#define MIPS_CPU_MCHECK 0x00004000 /* Machine check exception */ +#define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */ +#define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */ +#define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */ +#define MIPS_CPU_SUBSET_CACHES 0x00040000 /* P-cache subset enforced */ +#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ +#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ +#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ /* * CPU ASE encodings diff --git a/include/asm-mips/mach-ip22/cpu-feature-overrides.h b/include/asm-mips/mach-ip22/cpu-feature-overrides.h index ac71b4d6510a..ab9714668177 100644 --- a/include/asm-mips/mach-ip22/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip22/cpu-feature-overrides.h @@ -13,7 +13,7 @@ */ #define cpu_has_tlb 1 #define cpu_has_4kex 1 -#define cpu_has_4ktlb 1 +#define cpu_has_4kcache 1 #define cpu_has_fpu 1 #define cpu_has_32fpr 1 #define cpu_has_counter 1 diff --git a/include/asm-mips/mach-mips/cpu-feature-overrides.h b/include/asm-mips/mach-mips/cpu-feature-overrides.h index 98927f8b5f6d..5c5edbf93707 100644 --- a/include/asm-mips/mach-mips/cpu-feature-overrides.h +++ b/include/asm-mips/mach-mips/cpu-feature-overrides.h @@ -17,7 +17,7 @@ #ifdef CONFIG_CPU_MIPS32_R1 #define cpu_has_tlb 1 #define cpu_has_4kex 1 -#define cpu_has_4ktlb 1 +#define cpu_has_4kcache 1 /* #define cpu_has_fpu ? */ /* #define cpu_has_32fpr ? */ #define cpu_has_counter 1 @@ -43,7 +43,7 @@ #ifdef CONFIG_CPU_MIPS64_R1 #define cpu_has_tlb 1 #define cpu_has_4kex 1 -#define cpu_has_4ktlb 1 +#define cpu_has_4kcache 1 /* #define cpu_has_fpu ? */ /* #define cpu_has_32fpr ? */ #define cpu_has_counter 1 diff --git a/include/asm-mips/mach-rm200/cpu-feature-overrides.h b/include/asm-mips/mach-rm200/cpu-feature-overrides.h index 9b2a40524679..79f9b064c864 100644 --- a/include/asm-mips/mach-rm200/cpu-feature-overrides.h +++ b/include/asm-mips/mach-rm200/cpu-feature-overrides.h @@ -14,7 +14,7 @@ #define cpu_has_tlb 1 #define cpu_has_4kex 1 -#define cpu_has_4ktlb 1 +#define cpu_has_4kcache 1 #define cpu_has_fpu 1 #define cpu_has_32fpr 1 #define cpu_has_counter 1 diff --git a/include/asm-mips/mach-sim/cpu-feature-overrides.h b/include/asm-mips/mach-sim/cpu-feature-overrides.h index 09457217a57d..cadbe8eda79c 100644 --- a/include/asm-mips/mach-sim/cpu-feature-overrides.h +++ b/include/asm-mips/mach-sim/cpu-feature-overrides.h @@ -16,7 +16,7 @@ #ifdef CONFIG_CPU_MIPS32 #define cpu_has_tlb 1 #define cpu_has_4kex 1 -#define cpu_has_4ktlb 1 +#define cpu_has_4kcache 1 #define cpu_has_fpu 0 /* #define cpu_has_32fpr ? */ #define cpu_has_counter 1 @@ -41,7 +41,7 @@ #ifdef CONFIG_CPU_MIPS64 #define cpu_has_tlb 1 #define cpu_has_4kex 1 -#define cpu_has_4ktlb 1 +#define cpu_has_4kcache 1 /* #define cpu_has_fpu ? */ /* #define cpu_has_32fpr ? */ #define cpu_has_counter 1 |
