diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf548')
-rw-r--r-- | include/asm-blackfin/mach-bf548/anomaly.h | 54 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/bf548.h | 34 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/bfin_serial_5xx.h | 2 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/cdefBF54x_base.h | 33 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/defBF542.h | 4 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/defBF544.h | 2 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/defBF548.h | 6 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/defBF549.h | 2 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/defBF54x_base.h | 55 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/irq.h | 8 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/mem_init.h | 62 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/mem_map.h | 18 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/portmux.h | 16 |
13 files changed, 205 insertions, 91 deletions
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index c5b63759cdee..850dc12eb7f2 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -7,7 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision C, July 16, 2007; ADSP-BF549 Silicon Anomaly List + * - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -26,47 +26,59 @@ /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) /* False Hardware Error Exception when ISR context is not restored */ -#define ANOMALY_05000281 (1) +#define ANOMALY_05000281 (__SILICON_REVISION__ < 1) /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ -#define ANOMALY_05000304 (1) +#define ANOMALY_05000304 (__SILICON_REVISION__ < 1) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (1) +#define ANOMALY_05000312 (__SILICON_REVISION__ < 1) /* TWI Slave Boot Mode Is Not Functional */ -#define ANOMALY_05000324 (1) +#define ANOMALY_05000324 (__SILICON_REVISION__ < 1) /* External FIFO Boot Mode Is Not Functional */ -#define ANOMALY_05000325 (1) +#define ANOMALY_05000325 (__SILICON_REVISION__ < 1) /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ -#define ANOMALY_05000327 (1) +#define ANOMALY_05000327 (__SILICON_REVISION__ < 1) /* Incorrect Access of OTP_STATUS During otp_write() Function */ -#define ANOMALY_05000328 (1) +#define ANOMALY_05000328 (__SILICON_REVISION__ < 1) /* Synchronous Burst Flash Boot Mode Is Not Functional */ -#define ANOMALY_05000329 (1) +#define ANOMALY_05000329 (__SILICON_REVISION__ < 1) /* Host DMA Boot Mode Is Not Functional */ -#define ANOMALY_05000330 (1) +#define ANOMALY_05000330 (__SILICON_REVISION__ < 1) /* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ -#define ANOMALY_05000334 (1) +#define ANOMALY_05000334 (__SILICON_REVISION__ < 1) /* Inadequate Rotary Debounce Logic Duration */ -#define ANOMALY_05000335 (1) +#define ANOMALY_05000335 (__SILICON_REVISION__ < 1) /* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ -#define ANOMALY_05000336 (1) +#define ANOMALY_05000336 (__SILICON_REVISION__ < 1) /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ -#define ANOMALY_05000337 (1) +#define ANOMALY_05000337 (__SILICON_REVISION__ < 1) /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ -#define ANOMALY_05000338 (1) +#define ANOMALY_05000338 (__SILICON_REVISION__ < 1) /* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ -#define ANOMALY_05000340 (1) +#define ANOMALY_05000340 (__SILICON_REVISION__ < 1) /* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ -#define ANOMALY_05000344 (1) +#define ANOMALY_05000344 (__SILICON_REVISION__ < 1) /* USB Calibration Value Is Not Intialized */ -#define ANOMALY_05000346 (1) +#define ANOMALY_05000346 (__SILICON_REVISION__ < 1) /* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ -#define ANOMALY_05000347 (1) +#define ANOMALY_05000347 (__SILICON_REVISION__ < 1) /* Data Lost when Core Reads SDH Data FIFO */ -#define ANOMALY_05000349 (1) +#define ANOMALY_05000349 (__SILICON_REVISION__ < 1) /* PLL Status Register Is Inaccurate */ -#define ANOMALY_05000351 (1) +#define ANOMALY_05000351 (__SILICON_REVISION__ < 1) +/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ +#define ANOMALY_05000357 (1) +/* External Memory Read Access Hangs Core With PLL Bypass */ +#define ANOMALY_05000360 (1) +/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ +#define ANOMALY_05000365 (1) +/* Addressing Conflict between Boot ROM and Asynchronous Memory */ +#define ANOMALY_05000369 (1) +/* Mobile DDR Operation Not Functional */ +#define ANOMALY_05000377 (1) +/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ +#define ANOMALY_05000378 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h index 7e6d349beb08..e748588e8930 100644 --- a/include/asm-blackfin/mach-bf548/bf548.h +++ b/include/asm-blackfin/mach-bf548/bf548.h @@ -106,24 +106,22 @@ #define AMGCTLVAL (V_AMBEN | V_AMCKEN) -#ifdef CONFIG_BF542 -#define CPU "BF542" -#define CPUID 0x027c8000 -#endif -#ifdef CONFIG_BF544 -#define CPU "BF544" -#define CPUID 0x027c8000 -#endif -#ifdef CONFIG_BF548 -#define CPU "BF548" -#define CPUID 0x027c6000 -#endif -#ifdef CONFIG_BF549 -#define CPU "BF549" -#endif -#ifndef CPU -#define CPU "UNKNOWN" -#define CPUID 0x0 +#if defined(CONFIG_BF542) +# define CPU "BF542" +# define CPUID 0x027c8000 +#elif defined(CONFIG_BF544) +# define CPU "BF544" +# define CPUID 0x027c8000 +#elif defined(CONFIG_BF547) +# define CPU "BF547" +#elif defined(CONFIG_BF548) +# define CPU "BF548" +# define CPUID 0x027c6000 +#elif defined(CONFIG_BF549) +# define CPU "BF549" +#else +# define CPU "UNKNOWN" +# define CPUID 0x0 #endif #endif /* __MACH_BF48_H__ */ diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h index f21a1620e6bd..3770aa38ee9f 100644 --- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h @@ -186,7 +186,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart) if (uart->rts_pin >= 0) { gpio_request(uart->rts_pin, DRIVER_NAME); - gpio_direction_output(uart->rts_pin); + gpio_direction_output(uart->rts_pin, 0); } #endif } diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h index aefab3f618c1..19ddcd83c71f 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h @@ -244,39 +244,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) #define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) -#define bfin_read_TWI_CLKDIV() bfin_read16(TWI0_CLKDIV) -#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) -#define bfin_read_TWI_CONTROL() bfin_read16(TWI0_CONTROL) -#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI0_CONTROL, val) -#define bfin_read_TWI_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL) -#define bfin_write_TWI_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val) -#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) -#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) -#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) -#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) -#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI0_MASTER_CTRL) -#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTRL, val) -#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) -#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) -#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) -#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) -#define bfin_read_TWI_INT_STAT() bfin_read16(TWI0_INT_STAT) -#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) -#define bfin_read_TWI_INT_MASK() bfin_read16(TWI0_INT_MASK) -#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) -#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI0_FIFO_CTRL) -#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTRL, val) -#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) -#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) -#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) -#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) -#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) -#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) -#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) -#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) -#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) -#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) - /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ /* SPORT1 Registers */ diff --git a/include/asm-blackfin/mach-bf548/defBF542.h b/include/asm-blackfin/mach-bf548/defBF542.h index 32d07130200c..a7c809f29ede 100644 --- a/include/asm-blackfin/mach-bf548/defBF542.h +++ b/include/asm-blackfin/mach-bf548/defBF542.h @@ -432,8 +432,8 @@ #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ -#define CMD_TIMEOUT 0x4 /* CMD Time Out */ -#define DAT_TIMEOUT 0x8 /* Data Time Out */ +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ #define TX_UNDERRUN 0x10 /* Transmit Underrun */ #define RX_OVERRUN 0x20 /* Receive Overrun */ #define CMD_RESP_END 0x40 /* CMD Response End */ diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h index 760307e34b9e..b8b9870e2697 100644 --- a/include/asm-blackfin/mach-bf548/defBF544.h +++ b/include/asm-blackfin/mach-bf548/defBF544.h @@ -645,7 +645,7 @@ /* Bit masks for HOST_STATUS */ -#define READY 0x1 /* DMA Ready */ +#define DMA_READY 0x1 /* DMA Ready */ #define FIFOFULL 0x2 /* FIFO Full */ #define FIFOEMPTY 0x4 /* FIFO Empty */ #define COMPLETE 0x8 /* DMA Complete */ diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h index 70af33c963b0..e46f56891e6a 100644 --- a/include/asm-blackfin/mach-bf548/defBF548.h +++ b/include/asm-blackfin/mach-bf548/defBF548.h @@ -1007,7 +1007,7 @@ /* Bit masks for HOST_STATUS */ -#define READY 0x1 /* DMA Ready */ +#define DMA_READY 0x1 /* DMA Ready */ #define FIFOFULL 0x2 /* FIFO Full */ #define FIFOEMPTY 0x4 /* FIFO Empty */ #define COMPLETE 0x8 /* DMA Complete */ @@ -1095,8 +1095,8 @@ #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ -#define CMD_TIMEOUT 0x4 /* CMD Time Out */ -#define DAT_TIMEOUT 0x8 /* Data Time Out */ +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ #define TX_UNDERRUN 0x10 /* Transmit Underrun */ #define RX_OVERRUN 0x20 /* Receive Overrun */ #define CMD_RESP_END 0x40 /* CMD Response End */ diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h index 4e46d657e50e..fcb72b41e007 100644 --- a/include/asm-blackfin/mach-bf548/defBF549.h +++ b/include/asm-blackfin/mach-bf548/defBF549.h @@ -1671,7 +1671,7 @@ /* Bit masks for MXVR_DMAx_CONFIG */ #define MDMAEN 0x1 /* DMA Channel Enable */ -#define DD 0x2 /* DMA Channel Direction */ +#define DMADD 0x2 /* DMA Channel Direction */ #define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */ #define LCHAN 0x3c0 /* DMA Channel Logical Channel */ #define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */ diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h index 1d365c844ffe..08f90c21fe8a 100644 --- a/include/asm-blackfin/mach-bf548/defBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h @@ -1644,8 +1644,25 @@ #define RESTART 0x20 /* Work Unit Transitions */ #define DI_SEL 0x40 /* Data Interrupt Timing Select */ #define DI_EN 0x80 /* Data Interrupt Enable */ + #define NDSIZE 0xf00 /* Flex Descriptor Size */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ +#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ +#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ +#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ +#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ +#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ +#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ +#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ +#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ + #define DMAFLOW 0xf000 /* Next Operation */ +#define DMAFLOW_STOP 0x0000 /* Stop Mode */ +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ +#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ +#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ +#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ /* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ @@ -1755,17 +1772,36 @@ #define TRP 0x3c0000 /* Pre charge-to-active command period */ #define TRAS 0x3c00000 /* Min Active-to-pre charge time */ #define TRC 0x3c000000 /* Active-to-active time */ +#define DDR_TRAS(x) ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */ +#define DDR_TRP(x) ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */ +#define DDR_TRC(x) ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */ +#define DDR_TRFC(x) ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */ +#define DDR_TREFI(x) (x&TREFI) /* DDR tRFC = (1~15) cycles */ /* Bit masks for EBIU_DDRCTL1 */ #define TRCD 0xf /* Active-to-Read/write delay */ -#define MRD 0xf0 /* Mode register set to active */ +#define TMRD 0xf0 /* Mode register set to active */ #define TWR 0x300 /* Write Recovery time */ #define DDRDATWIDTH 0x3000 /* DDR data width */ #define EXTBANKS 0xc000 /* External banks */ #define DDRDEVWIDTH 0x30000 /* DDR device width */ #define DDRDEVSIZE 0xc0000 /* DDR device size */ -#define TWWTR 0xf0000000 /* Write-to-read delay */ +#define TWTR 0xf0000000 /* Write-to-read delay */ +#define DDR_TWTR(x) ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */ +#define DDR_TMRD(x) ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */ +#define DDR_TWR(x) ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */ +#define DDR_TRCD(x) (x&TRCD) /* DDR tRCD = (1~15) cycles */ +#define DDR_DATWIDTH 0x2000 /* DDR data width */ +#define EXTBANK_1 0 /* 1 external bank */ +#define EXTBANK_2 0x4000 /* 2 external banks */ +#define DEVSZ_64 0x40000 /* DDR External Bank Size = 64MB */ +#define DEVSZ_128 0x80000 /* DDR External Bank Size = 128MB */ +#define DEVSZ_256 0xc0000 /* DDR External Bank Size = 256MB */ +#define DEVSZ_512 0 /* DDR External Bank Size = 512MB */ +#define DEVWD_4 0 /* DDR Device Width = 4 Bits */ +#define DEVWD_8 0x10000 /* DDR Device Width = 8 Bits */ +#define DEVWD_16 0x20000 /* DDR Device Width = 16 Bits */ /* Bit masks for EBIU_DDRCTL2 */ @@ -1773,6 +1809,10 @@ #define CASLATENCY 0x70 /* CAS latency */ #define DLLRESET 0x100 /* DLL Reset */ #define REGE 0x1000 /* Register mode enable */ +#define CL_1_5 0x50 /* DDR CAS Latency = 1.5 cycles */ +#define CL_2 0x20 /* DDR CAS Latency = 2 cycles */ +#define CL_2_5 0x60 /* DDR CAS Latency = 2.5 cycles */ +#define CL_3 0x30 /* DDR CAS Latency = 3 cycles */ /* Bit masks for EBIU_DDRCTL3 */ @@ -2240,6 +2280,10 @@ #define CSEL 0x30 /* Core Select */ #define SSEL 0xf /* System Select */ +#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ +#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ +#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ +#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ /* Bit masks for PLL_CTL */ @@ -2252,6 +2296,13 @@ #define PLL_OFF 0x2 /* Disable PLL */ #define DF 0x1 /* Divide Frequency */ +/* SWRST Masks */ +#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ +#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ +#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ +#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ +#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ + /* Bit masks for PLL_STAT */ #define PLL_LOCKED 0x20 /* PLL Locked Status */ diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h index 3b08cf9bd6f3..c34507a3f1df 100644 --- a/include/asm-blackfin/mach-bf548/irq.h +++ b/include/asm-blackfin/mach-bf548/irq.h @@ -88,7 +88,7 @@ Events (highest priority) EMU 0 #define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */ #define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */ #define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */ -#define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */ +#define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */ #define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ #define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ #define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ @@ -338,11 +338,7 @@ Events (highest priority) EMU 0 #define GPIO_IRQ_BASE IRQ_PA0 -#ifdef CONFIG_IRQCHIP_DEMUX_GPIO #define NR_IRQS (IRQ_PJ15+1) -#else -#define NR_IRQS (SYS_IRQS+1) -#endif /* For compatibility reasons with existing code */ @@ -410,7 +406,7 @@ Events (highest priority) EMU 0 #define IRQ_PINT1_POS 16 #define IRQ_MDMAS0_POS 20 #define IRQ_MDMAS1_POS 24 -#define IRQ_WATCHDOG_POS 28 +#define IRQ_WATCH_POS 28 /* IAR3 BIT FIELDS */ #define IRQ_DMAC1_ERR_POS 0 diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h index 0cb279e973d7..befc2903d5a5 100644 --- a/include/asm-blackfin/mach-bf548/mem_init.h +++ b/include/asm-blackfin/mach-bf548/mem_init.h @@ -28,8 +28,68 @@ * If not, write to the Free Software Foundation, * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1) + +#if (CONFIG_MEM_MT46V32M16_6T) +#define DDR_SIZE DEVSZ_512 +#define DDR_WIDTH DEVWD_16 + +#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60)) +#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42)) +#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) +#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72)) +#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800)) + +#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) +#define DDR_tWTR DDR_TWTR(1) +#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12)) +#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) +#endif + +#if (CONFIG_MEM_MT46V32M16_5B) +#define DDR_SIZE DEVSZ_512 +#define DDR_WIDTH DEVWD_16 + +#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55)) +#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40)) +#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) +#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70)) +#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800)) + +#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) +#define DDR_tWTR DDR_TWTR(2) +#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10)) +#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) +#endif + +#if (CONFIG_MEM_GENERIC_BOARD) +#define DDR_SIZE DEVSZ_512 +#define DDR_WIDTH DEVWD_16 + +#define DDR_tRCD DDR_TRCD(3) +#define DDR_tWTR DDR_TWTR(2) +#define DDR_tWR DDR_TWR(2) +#define DDR_tMRD DDR_TMRD(2) +#define DDR_tRP DDR_TRP(3) +#define DDR_tRAS DDR_TRAS(7) +#define DDR_tRC DDR_TRC(10) +#define DDR_tRFC DDR_TRFC(12) +#define DDR_tREFI DDR_TREFI(1288) +#endif + +#if (CONFIG_SCLK_HZ <= 133333333) +#define DDR_CL CL_2 +#elif (CONFIG_SCLK_HZ <= 166666666) +#define DDR_CL CL_2_5 +#else +#define DDR_CL CL_3 +#endif + +#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI) +#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \ + | DDR_tMRD | DDR_tWR | DDR_tRCD) +#define mem_DDRCTL2 DDR_CL -#if (CONFIG_MEM_MT46V32M16) #if defined CONFIG_CLKIN_HALF #define CLKIN_HALF 1 diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h index ec1597e31831..f99f47bc3a07 100644 --- a/include/asm-blackfin/mach-bf548/mem_map.h +++ b/include/asm-blackfin/mach-bf548/mem_map.h @@ -47,6 +47,12 @@ /* Boot ROM Memory */ #define BOOT_ROM_START 0xEF000000 +#define BOOT_ROM_LENGTH 0x1000 + +/* L1 Instruction ROM */ + +#define L1_ROM_START 0xFFA14000 +#define L1_ROM_LENGTH 0x10000 /* Level 1 Memory */ @@ -87,11 +93,19 @@ #define BFIN_DSUPBANKS 0 #endif /*CONFIG_BFIN_DCACHE*/ +/* Level 2 Memory */ +#if !defined(CONFIG_BF542) +# define L2_START 0xFEB00000 +# if defined(CONFIG_BF544) +# define L2_LENGTH 0x10000 +# else +# define L2_LENGTH 0x20000 +# endif +#endif + /* Scratch Pad Memory */ -#if defined(CONFIG_BF54x) #define L1_SCRATCH_START 0xFFB00000 #define L1_SCRATCH_LENGTH 0x1000 -#endif #endif/* _MEM_MAP_548_H_ */ diff --git a/include/asm-blackfin/mach-bf548/portmux.h b/include/asm-blackfin/mach-bf548/portmux.h index b382deb501a7..8177a567dcdb 100644 --- a/include/asm-blackfin/mach-bf548/portmux.h +++ b/include/asm-blackfin/mach-bf548/portmux.h @@ -1,6 +1,8 @@ #ifndef _MACH_PORTMUX_H_ #define _MACH_PORTMUX_H_ +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + #define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0)) #define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0)) #define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0)) @@ -267,4 +269,18 @@ #define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0)) #define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0)) + +#define P_NAND_D0 (P_DONTCARE) +#define P_NAND_D1 (P_DONTCARE) +#define P_NAND_D2 (P_DONTCARE) +#define P_NAND_D3 (P_DONTCARE) +#define P_NAND_D4 (P_DONTCARE) +#define P_NAND_D5 (P_DONTCARE) +#define P_NAND_D6 (P_DONTCARE) +#define P_NAND_D7 (P_DONTCARE) +#define P_NAND_WE (P_DONTCARE) +#define P_NAND_RE (P_DONTCARE) +#define P_NAND_CLE (P_DONTCARE) +#define P_NAND_ALE (P_DONTCARE) + #endif /* _MACH_PORTMUX_H_ */ |