diff options
Diffstat (limited to 'arch/arm/mach-s3c2410/include')
48 files changed, 0 insertions, 4080 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/anubis-cpld.h b/arch/arm/mach-s3c2410/include/mach/anubis-cpld.h deleted file mode 100644 index 1b614d5a81f3..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/anubis-cpld.h +++ /dev/null @@ -1,25 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/anubis-cpld.h - * - * Copyright (c) 2005 Simtec Electronics - * http://www.simtec.co.uk/products/ - * Ben Dooks <ben@simtec.co.uk> - * - * ANUBIS - CPLD control constants - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_ANUBISCPLD_H -#define __ASM_ARCH_ANUBISCPLD_H - -/* CTRL2 - NAND WP control, IDE Reset assert/check */ - -#define ANUBIS_CTRL1_NANDSEL (0x3) - -/* IDREG - revision */ - -#define ANUBIS_IDREG_REVMASK (0x7) - -#endif /* __ASM_ARCH_ANUBISCPLD_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/anubis-irq.h b/arch/arm/mach-s3c2410/include/mach/anubis-irq.h deleted file mode 100644 index a2a328134e34..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/anubis-irq.h +++ /dev/null @@ -1,21 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/anubis-irq.h - * - * Copyright (c) 2005 Simtec Electronics - * http://www.simtec.co.uk/products/ - * Ben Dooks <ben@simtec.co.uk> - * - * ANUBIS - IRQ Number definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_ANUBISIRQ_H -#define __ASM_ARCH_ANUBISIRQ_H - -#define IRQ_IDE0 IRQ_EINT2 -#define IRQ_IDE1 IRQ_EINT3 -#define IRQ_ASIX IRQ_EINT1 - -#endif /* __ASM_ARCH_ANUBISIRQ_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/anubis-map.h b/arch/arm/mach-s3c2410/include/mach/anubis-map.h deleted file mode 100644 index c9deb3a5b2c3..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/anubis-map.h +++ /dev/null @@ -1,38 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/anubis-map.h - * - * Copyright (c) 2005 Simtec Electronics - * http://www.simtec.co.uk/products/ - * Ben Dooks <ben@simtec.co.uk> - * - * ANUBIS - Memory map definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* needs arch/map.h including with this */ - -#ifndef __ASM_ARCH_ANUBISMAP_H -#define __ASM_ARCH_ANUBISMAP_H - -/* start peripherals off after the S3C2410 */ - -#define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000)) - -#define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26)) - -/* we put the CPLD registers next, to get them out of the way */ - -#define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) /* 0x01800000 */ -#define ANUBIS_PA_CTRL1 (ANUBIS_PA_CPLD) - -#define ANUBIS_VA_IDREG ANUBIS_IOADDR(0x00300000) /* 0x01B00000 */ -#define ANUBIS_PA_IDREG (ANUBIS_PA_CPLD + (3<<23)) - -#define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000) -#define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000) -#define ANUBIS_IDESEC ANUBIS_IOADDR(0x01200000) -#define ANUBIS_IDESECAUX ANUBIS_IOADDR(0x01300000) - -#endif /* __ASM_ARCH_ANUBISMAP_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/bast-cpld.h b/arch/arm/mach-s3c2410/include/mach/bast-cpld.h deleted file mode 100644 index bee2a7a932a0..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/bast-cpld.h +++ /dev/null @@ -1,53 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/bast-cpld.h - * - * Copyright (c) 2003-2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * BAST - CPLD control constants - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_BASTCPLD_H -#define __ASM_ARCH_BASTCPLD_H - -/* CTRL1 - Audio LR routing */ - -#define BAST_CPLD_CTRL1_LRCOFF (0x00) -#define BAST_CPLD_CTRL1_LRCADC (0x01) -#define BAST_CPLD_CTRL1_LRCDAC (0x02) -#define BAST_CPLD_CTRL1_LRCARM (0x03) -#define BAST_CPLD_CTRL1_LRMASK (0x03) - -/* CTRL2 - NAND WP control, IDE Reset assert/check */ - -#define BAST_CPLD_CTRL2_WNAND (0x04) -#define BAST_CPLD_CTLR2_IDERST (0x08) - -/* CTRL3 - rom write control, CPLD identity */ - -#define BAST_CPLD_CTRL3_IDMASK (0x0e) -#define BAST_CPLD_CTRL3_ROMWEN (0x01) - -/* CTRL4 - 8bit LCD interface control/status */ - -#define BAST_CPLD_CTRL4_LLAT (0x01) -#define BAST_CPLD_CTRL4_LCDRW (0x02) -#define BAST_CPLD_CTRL4_LCDCMD (0x04) -#define BAST_CPLD_CTRL4_LCDE2 (0x01) - -/* CTRL5 - DMA routing */ - -#define BAST_CPLD_DMA0_PRIIDE (0<<0) -#define BAST_CPLD_DMA0_SECIDE (1<<0) -#define BAST_CPLD_DMA0_ISA15 (2<<0) -#define BAST_CPLD_DMA0_ISA36 (3<<0) - -#define BAST_CPLD_DMA1_PRIIDE (0<<2) -#define BAST_CPLD_DMA1_SECIDE (1<<2) -#define BAST_CPLD_DMA1_ISA15 (2<<2) -#define BAST_CPLD_DMA1_ISA36 (3<<2) - -#endif /* __ASM_ARCH_BASTCPLD_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/bast-irq.h b/arch/arm/mach-s3c2410/include/mach/bast-irq.h deleted file mode 100644 index cac428c42e7f..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/bast-irq.h +++ /dev/null @@ -1,29 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/bast-irq.h - * - * Copyright (c) 2003-2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Machine BAST - IRQ Number definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_BASTIRQ_H -#define __ASM_ARCH_BASTIRQ_H - -/* irq numbers to onboard peripherals */ - -#define IRQ_USBOC IRQ_EINT18 -#define IRQ_IDE0 IRQ_EINT16 -#define IRQ_IDE1 IRQ_EINT17 -#define IRQ_PCSERIAL1 IRQ_EINT15 -#define IRQ_PCSERIAL2 IRQ_EINT14 -#define IRQ_PCPARALLEL IRQ_EINT13 -#define IRQ_ASIX IRQ_EINT11 -#define IRQ_DM9000 IRQ_EINT10 -#define IRQ_ISA IRQ_EINT9 -#define IRQ_SMALERT IRQ_EINT8 - -#endif /* __ASM_ARCH_BASTIRQ_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/bast-map.h b/arch/arm/mach-s3c2410/include/mach/bast-map.h deleted file mode 100644 index 6e7dc9d0cf0e..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/bast-map.h +++ /dev/null @@ -1,146 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/bast-map.h - * - * Copyright (c) 2003-2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Machine BAST - Memory map definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* needs arch/map.h including with this */ - -/* ok, we've used up to 0x13000000, now we need to find space for the - * peripherals that live in the nGCS[x] areas, which are quite numerous - * in their space. We also have the board's CPLD to find register space - * for. - */ - -#ifndef __ASM_ARCH_BASTMAP_H -#define __ASM_ARCH_BASTMAP_H - -#define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000)) - -/* we put the CPLD registers next, to get them out of the way */ - -#define BAST_VA_CTRL1 BAST_IOADDR(0x00000000) /* 0x01300000 */ -#define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000) - -#define BAST_VA_CTRL2 BAST_IOADDR(0x00100000) /* 0x01400000 */ -#define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000) - -#define BAST_VA_CTRL3 BAST_IOADDR(0x00200000) /* 0x01500000 */ -#define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000) - -#define BAST_VA_CTRL4 BAST_IOADDR(0x00300000) /* 0x01600000 */ -#define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000) - -/* next, we have the PC104 ISA interrupt registers */ - -#define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */ -#define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000) - -#define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */ -#define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000) - -#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */ -#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000) - -#define BAST_PA_LCD_RCMD1 (0x8800000) -#define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000) - -#define BAST_PA_LCD_WCMD1 (0x8000000) -#define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000) - -#define BAST_PA_LCD_RDATA1 (0x9800000) -#define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000) - -#define BAST_PA_LCD_WDATA1 (0x9000000) -#define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000) - -#define BAST_PA_LCD_RCMD2 (0xA800000) -#define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000) - -#define BAST_PA_LCD_WCMD2 (0xA000000) -#define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000) - -#define BAST_PA_LCD_RDATA2 (0xB800000) -#define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000) - -#define BAST_PA_LCD_WDATA2 (0xB000000) -#define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000) - - -/* 0xE0000000 contains the IO space that is split by speed and - * wether the access is for 8 or 16bit IO... this ensures that - * the correct access is made - * - * 0x10000000 of space, partitioned as so: - * - * 0x00000000 to 0x04000000 8bit, slow - * 0x04000000 to 0x08000000 16bit, slow - * 0x08000000 to 0x0C000000 16bit, net - * 0x0C000000 to 0x10000000 16bit, fast - * - * each of these spaces has the following in: - * - * 0x00000000 to 0x01000000 16MB ISA IO space - * 0x01000000 to 0x02000000 16MB ISA memory space - * 0x02000000 to 0x02100000 1MB IDE primary channel - * 0x02100000 to 0x02200000 1MB IDE primary channel aux - * 0x02200000 to 0x02400000 1MB IDE secondary channel - * 0x02300000 to 0x02400000 1MB IDE secondary channel aux - * 0x02400000 to 0x02500000 1MB ASIX ethernet controller - * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller - * 0x02600000 to 0x02700000 1MB PC SuperIO controller - * - * the phyiscal layout of the zones are: - * nGCS2 - 8bit, slow - * nGCS3 - 16bit, slow - * nGCS4 - 16bit, net - * nGCS5 - 16bit, fast - */ - -#define BAST_VA_MULTISPACE (0xE0000000) - -#define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000) -#define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000) -#define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000) -#define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000) -#define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000) -#define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000) -#define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000) -#define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000) -#define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000) - -#define BAST_VA_MULTISPACE (0xE0000000) - -#define BAST_VAM_CS2 (0x00000000) -#define BAST_VAM_CS3 (0x04000000) -#define BAST_VAM_CS4 (0x08000000) -#define BAST_VAM_CS5 (0x0C000000) - -/* physical offset addresses for the peripherals */ - -#define BAST_PA_ISAIO (0x00000000) -#define BAST_PA_ASIXNET (0x01000000) -#define BAST_PA_SUPERIO (0x01800000) -#define BAST_PA_IDEPRI (0x02000000) -#define BAST_PA_IDEPRIAUX (0x02800000) -#define BAST_PA_IDESEC (0x03000000) -#define BAST_PA_IDESECAUX (0x03800000) -#define BAST_PA_ISAMEM (0x04000000) -#define BAST_PA_DM9000 (0x05000000) - -/* some configurations for the peripherals */ - -#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2) -/* */ - -#define BAST_ASIXNET_CS BAST_VAM_CS5 -#define BAST_IDE_CS BAST_VAM_CS5 -#define BAST_DM9000_CS BAST_VAM_CS4 - -#endif /* __ASM_ARCH_BASTMAP_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/bast-pmu.h b/arch/arm/mach-s3c2410/include/mach/bast-pmu.h deleted file mode 100644 index 4c38b39b741d..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/bast-pmu.h +++ /dev/null @@ -1,40 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/bast-pmu.h - * - * Copyright (c) 2003-2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * Vincent Sanders <vince@simtec.co.uk> - * - * Machine BAST - Power Management chip - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_BASTPMU_H -#define __ASM_ARCH_BASTPMU_H "08_OCT_2004" - -#define BASTPMU_REG_IDENT (0x00) -#define BASTPMU_REG_VERSION (0x01) -#define BASTPMU_REG_DDCCTRL (0x02) -#define BASTPMU_REG_POWER (0x03) -#define BASTPMU_REG_RESET (0x04) -#define BASTPMU_REG_GWO (0x05) -#define BASTPMU_REG_WOL (0x06) -#define BASTPMU_REG_WOR (0x07) -#define BASTPMU_REG_UID (0x09) - -#define BASTPMU_EEPROM (0xC0) - -#define BASTPMU_EEP_UID (BASTPMU_EEPROM + 0) -#define BASTPMU_EEP_WOL (BASTPMU_EEPROM + 8) -#define BASTPMU_EEP_WOR (BASTPMU_EEPROM + 9) - -#define BASTPMU_IDENT_0 0x53 -#define BASTPMU_IDENT_1 0x42 -#define BASTPMU_IDENT_2 0x50 -#define BASTPMU_IDENT_3 0x4d - -#define BASTPMU_RESET_GUARD (0x55) - -#endif /* __ASM_ARCH_BASTPMU_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/debug-macro.S b/arch/arm/mach-s3c2410/include/mach/debug-macro.S deleted file mode 100644 index 4135de87d1f7..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/debug-macro.S +++ /dev/null @@ -1,101 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Copyright (C) 2005 Simtec Electronics - * - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <mach/map.h> -#include <mach/regs-gpio.h> -#include <plat/regs-serial.h> - -#define S3C2410_UART1_OFF (0x4000) -#define SHIFT_2440TXF (14-9) - - .macro addruart, rp, rv, tmp - ldr \rp, = S3C24XX_PA_UART - ldr \rv, = S3C24XX_VA_UART -#if CONFIG_DEBUG_S3C_UART != 0 - add \rp, \rp, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART) - add \rv, \rv, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART) -#endif - .endm - - .macro fifo_full_s3c24xx rd, rx - @ check for arm920 vs arm926. currently assume all arm926 - @ devices have an 64 byte FIFO identical to the s3c2440 - mrc p15, 0, \rd, c0, c0 - and \rd, \rd, #0xff0 - teq \rd, #0x260 - beq 1004f - mrc p15, 0, \rd, c1, c0 - tst \rd, #1 - addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) - addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART) - bic \rd, \rd, #0xff000 - ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ] - and \rd, \rd, #0x00ff0000 - teq \rd, #0x00440000 @ is it 2440? -1004: - ldr \rd, [ \rx, # S3C2410_UFSTAT ] - moveq \rd, \rd, lsr #SHIFT_2440TXF - tst \rd, #S3C2410_UFSTAT_TXFULL - .endm - - .macro fifo_full_s3c2410 rd, rx - ldr \rd, [ \rx, # S3C2410_UFSTAT ] - tst \rd, #S3C2410_UFSTAT_TXFULL - .endm - -/* fifo level reading */ - - .macro fifo_level_s3c24xx rd, rx - @ check for arm920 vs arm926. currently assume all arm926 - @ devices have an 64 byte FIFO identical to the s3c2440 - mrc p15, 0, \rd, c0, c0 - and \rd, \rd, #0xff0 - teq \rd, #0x260 - beq 10000f - mrc p15, 0, \rd, c1, c0 - tst \rd, #1 - addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) - addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART) - bic \rd, \rd, #0xff000 - ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ] - and \rd, \rd, #0x00ff0000 - teq \rd, #0x00440000 @ is it 2440? - -10000: - ldr \rd, [ \rx, # S3C2410_UFSTAT ] - andne \rd, \rd, #S3C2410_UFSTAT_TXMASK - andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK - .endm - - .macro fifo_level_s3c2410 rd, rx - ldr \rd, [ \rx, # S3C2410_UFSTAT ] - and \rd, \rd, #S3C2410_UFSTAT_TXMASK - .endm - -/* Select the correct implementation depending on the configuration. The - * S3C2440 will get selected by default, as these are the most widely - * used variants of these -*/ - -#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY) -#define fifo_full fifo_full_s3c2410 -#define fifo_level fifo_level_s3c2410 -#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY) -#define fifo_full fifo_full_s3c24xx -#define fifo_level fifo_level_s3c24xx -#endif - -/* include the reset of the code which will do the work */ - -#include <plat/debug-macro.S> diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h deleted file mode 100644 index acbdfecd4186..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/dma.h +++ /dev/null @@ -1,210 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/dma.h - * - * Copyright (C) 2003-2006 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Samsung S3C24XX DMA support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_DMA_H -#define __ASM_ARCH_DMA_H __FILE__ - -#include <linux/device.h> - -#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ - -/* We use `virtual` dma channels to hide the fact we have only a limited - * number of DMA channels, and not of all of them (dependent on the device) - * can be attached to any DMA source. We therefore let the DMA core handle - * the allocation of hardware channels to clients. -*/ - -enum dma_ch { - DMACH_XD0, - DMACH_XD1, - DMACH_SDI, - DMACH_SPI0, - DMACH_SPI1, - DMACH_UART0, - DMACH_UART1, - DMACH_UART2, - DMACH_TIMER, - DMACH_I2S_IN, - DMACH_I2S_OUT, - DMACH_PCM_IN, - DMACH_PCM_OUT, - DMACH_MIC_IN, - DMACH_USB_EP1, - DMACH_USB_EP2, - DMACH_USB_EP3, - DMACH_USB_EP4, - DMACH_UART0_SRC2, /* s3c2412 second uart sources */ - DMACH_UART1_SRC2, - DMACH_UART2_SRC2, - DMACH_UART3, /* s3c2443 has extra uart */ - DMACH_UART3_SRC2, - DMACH_MAX, /* the end entry */ -}; - -static inline bool samsung_dma_has_circular(void) -{ - return false; -} - -static inline bool samsung_dma_is_dmadev(void) -{ - return false; -} - -#include <plat/dma.h> - -#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ - -/* we have 4 dma channels */ -#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416) -#define S3C_DMA_CHANNELS (4) -#else -#define S3C_DMA_CHANNELS (6) -#endif - -/* types */ - -enum s3c2410_dma_state { - S3C2410_DMA_IDLE, - S3C2410_DMA_RUNNING, - S3C2410_DMA_PAUSED -}; - -/* enum s3c2410_dma_loadst - * - * This represents the state of the DMA engine, wrt to the loaded / running - * transfers. Since we don't have any way of knowing exactly the state of - * the DMA transfers, we need to know the state to make decisions on wether - * we can - * - * S3C2410_DMA_NONE - * - * There are no buffers loaded (the channel should be inactive) - * - * S3C2410_DMA_1LOADED - * - * There is one buffer loaded, however it has not been confirmed to be - * loaded by the DMA engine. This may be because the channel is not - * yet running, or the DMA driver decided that it was too costly to - * sit and wait for it to happen. - * - * S3C2410_DMA_1RUNNING - * - * The buffer has been confirmed running, and not finisged - * - * S3C2410_DMA_1LOADED_1RUNNING - * - * There is a buffer waiting to be loaded by the DMA engine, and one - * currently running. -*/ - -enum s3c2410_dma_loadst { - S3C2410_DMALOAD_NONE, - S3C2410_DMALOAD_1LOADED, - S3C2410_DMALOAD_1RUNNING, - S3C2410_DMALOAD_1LOADED_1RUNNING, -}; - - -/* flags */ - -#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about - * waiting for reloads */ -#define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */ - -#define S3C2410_DMAF_CIRCULAR (1 << 2) /* no circular dma support */ - -/* dma buffer */ - -struct s3c2410_dma_buf; - -/* s3c2410_dma_buf - * - * internally used buffer structure to describe a queued or running - * buffer. -*/ - -struct s3c2410_dma_buf { - struct s3c2410_dma_buf *next; - int magic; /* magic */ - int size; /* buffer size in bytes */ - dma_addr_t data; /* start of DMA data */ - dma_addr_t ptr; /* where the DMA got to [1] */ - void *id; /* client's id */ -}; - -/* [1] is this updated for both recv/send modes? */ - -struct s3c2410_dma_stats { - unsigned long loads; - unsigned long timeout_longest; - unsigned long timeout_shortest; - unsigned long timeout_avg; - unsigned long timeout_failed; -}; - -struct s3c2410_dma_map; - -/* struct s3c2410_dma_chan - * - * full state information for each DMA channel -*/ - -struct s3c2410_dma_chan { - /* channel state flags and information */ - unsigned char number; /* number of this dma channel */ - unsigned char in_use; /* channel allocated */ - unsigned char irq_claimed; /* irq claimed for channel */ - unsigned char irq_enabled; /* irq enabled for channel */ - unsigned char xfer_unit; /* size of an transfer */ - - /* channel state */ - - enum s3c2410_dma_state state; - enum s3c2410_dma_loadst load_state; - struct s3c2410_dma_client *client; - - /* channel configuration */ - enum dma_data_direction source; - enum dma_ch req_ch; - unsigned long dev_addr; - unsigned long load_timeout; - unsigned int flags; /* channel flags */ - - struct s3c24xx_dma_map *map; /* channel hw maps */ - - /* channel's hardware position and configuration */ - void __iomem *regs; /* channels registers */ - void __iomem *addr_reg; /* data address register */ - unsigned int irq; /* channel irq */ - unsigned long dcon; /* default value of DCON */ - - /* driver handles */ - s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */ - s3c2410_dma_opfn_t op_fn; /* channel op callback */ - - /* stats gathering */ - struct s3c2410_dma_stats *stats; - struct s3c2410_dma_stats stats_store; - - /* buffer list and information */ - struct s3c2410_dma_buf *curr; /* current dma buffer */ - struct s3c2410_dma_buf *next; /* next buffer to load */ - struct s3c2410_dma_buf *end; /* end of queue */ - - /* system device */ - struct device dev; -}; - -typedef unsigned long dma_device_t; - -#endif /* __ASM_ARCH_DMA_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/entry-macro.S b/arch/arm/mach-s3c2410/include/mach/entry-macro.S deleted file mode 100644 index 7615a14773fa..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/entry-macro.S +++ /dev/null @@ -1,70 +0,0 @@ -/* - * arch/arm/mach-s3c2410/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for S3C2410-based platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. -*/ - -/* We have a problem that the INTOFFSET register does not always - * show one interrupt. Occasionally we get two interrupts through - * the prioritiser, and this causes the INTOFFSET register to show - * what looks like the logical-or of the two interrupt numbers. - * - * Thanks to Klaus, Shannon, et al for helping to debug this problem -*/ - -#define INTPND (0x10) -#define INTOFFSET (0x14) - -#include <mach/hardware.h> -#include <asm/irq.h> - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - mov \base, #S3C24XX_VA_IRQ - - @@ try the interrupt offset register, since it is there - - ldr \irqstat, [ \base, #INTPND ] - teq \irqstat, #0 - beq 1002f - ldr \irqnr, [ \base, #INTOFFSET ] - mov \tmp, #1 - tst \irqstat, \tmp, lsl \irqnr - bne 1001f - - @@ the number specified is not a valid irq, so try - @@ and work it out for ourselves - - mov \irqnr, #0 @@ start here - - @@ work out which irq (if any) we got - - movs \tmp, \irqstat, lsl#16 - addeq \irqnr, \irqnr, #16 - moveq \irqstat, \irqstat, lsr#16 - tst \irqstat, #0xff - addeq \irqnr, \irqnr, #8 - moveq \irqstat, \irqstat, lsr#8 - tst \irqstat, #0xf - addeq \irqnr, \irqnr, #4 - moveq \irqstat, \irqstat, lsr#4 - tst \irqstat, #0x3 - addeq \irqnr, \irqnr, #2 - moveq \irqstat, \irqstat, lsr#2 - tst \irqstat, #0x1 - addeq \irqnr, \irqnr, #1 - - @@ we have the value -1001: - adds \irqnr, \irqnr, #IRQ_EINT0 -1002: - @@ exit here, Z flag unset if IRQ - - .endm diff --git a/arch/arm/mach-s3c2410/include/mach/fb.h b/arch/arm/mach-s3c2410/include/mach/fb.h deleted file mode 100644 index a957bc8ed44f..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/fb.h +++ /dev/null @@ -1 +0,0 @@ -#include <plat/fb-s3c2410.h> diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h deleted file mode 100644 index c53ad34c6579..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h +++ /dev/null @@ -1 +0,0 @@ -#include <plat/gpio-fns.h> diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h deleted file mode 100644 index 019ea86057f6..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h +++ /dev/null @@ -1,118 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/gpio-nrs.h - * - * Copyright (c) 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - GPIO bank numbering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __MACH_GPIONRS_H -#define __MACH_GPIONRS_H - -#define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) - -#define S3C2410_GPIO_BANKG (32*6) -#define S3C2410_GPIO_BANKH (32*7) - -/* GPIO sizes for various SoCs: - * - * 2442 - * 2410 2412 2440 2443 2416 - * ---- ---- ---- ---- ---- - * A 23 22 25 16 25 - * B 11 11 11 11 9 - * C 16 15 16 16 16 - * D 16 16 16 16 16 - * E 16 16 16 16 16 - * F 8 8 8 8 8 - * G 16 16 16 16 8 - * H 11 11 9 15 15 - * J -- -- 13 16 -- - * K -- -- -- -- 16 - * L -- -- -- 15 7 - * M -- -- -- 2 2 - */ - -/* GPIO bank sizes */ -#define S3C2410_GPIO_A_NR (32) -#define S3C2410_GPIO_B_NR (32) -#define S3C2410_GPIO_C_NR (32) -#define S3C2410_GPIO_D_NR (32) -#define S3C2410_GPIO_E_NR (32) -#define S3C2410_GPIO_F_NR (32) -#define S3C2410_GPIO_G_NR (32) -#define S3C2410_GPIO_H_NR (32) -#define S3C2410_GPIO_J_NR (32) /* technically 16. */ -#define S3C2410_GPIO_K_NR (32) /* technically 16. */ -#define S3C2410_GPIO_L_NR (32) /* technically 15. */ -#define S3C2410_GPIO_M_NR (32) /* technically 2. */ - -#if CONFIG_S3C_GPIO_SPACE != 0 -#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment -#endif - -#define S3C2410_GPIO_NEXT(__gpio) \ - ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0) - -#ifndef __ASSEMBLY__ - -enum s3c_gpio_number { - S3C2410_GPIO_A_START = 0, - S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A), - S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B), - S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C), - S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D), - S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E), - S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F), - S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G), - S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H), - S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J), - S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K), - S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L), -}; - -#endif /* __ASSEMBLY__ */ - -/* S3C2410 GPIO number definitions. */ - -#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr)) -#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr)) -#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr)) -#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr)) -#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr)) -#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr)) -#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr)) -#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr)) -#define S3C2410_GPJ(_nr) (S3C2410_GPIO_J_START + (_nr)) -#define S3C2410_GPK(_nr) (S3C2410_GPIO_K_START + (_nr)) -#define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr)) -#define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr)) - -/* compatibility until drivers can be modified */ - -#define S3C2410_GPA0 S3C2410_GPA(0) -#define S3C2410_GPA1 S3C2410_GPA(1) -#define S3C2410_GPA3 S3C2410_GPA(3) -#define S3C2410_GPA7 S3C2410_GPA(7) - -#define S3C2410_GPE0 S3C2410_GPE(0) -#define S3C2410_GPE1 S3C2410_GPE(1) -#define S3C2410_GPE2 S3C2410_GPE(2) -#define S3C2410_GPE3 S3C2410_GPE(3) -#define S3C2410_GPE4 S3C2410_GPE(4) -#define S3C2410_GPE5 S3C2410_GPE(5) -#define S3C2410_GPE6 S3C2410_GPE(6) -#define S3C2410_GPE7 S3C2410_GPE(7) -#define S3C2410_GPE8 S3C2410_GPE(8) -#define S3C2410_GPE9 S3C2410_GPE(9) -#define S3C2410_GPE10 S3C2410_GPE(10) - -#define S3C2410_GPH10 S3C2410_GPH(10) - -#endif /* __MACH_GPIONRS_H */ - diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-track.h b/arch/arm/mach-s3c2410/include/mach/gpio-track.h deleted file mode 100644 index c410a078622c..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/gpio-track.h +++ /dev/null @@ -1,33 +0,0 @@ -/* arch/arm/mach-s3c24100/include/mach/gpio-core.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C2410 - GPIO core support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_GPIO_CORE_H -#define __ASM_ARCH_GPIO_CORE_H __FILE__ - -#include <mach/regs-gpio.h> - -extern struct samsung_gpio_chip s3c24xx_gpios[]; - -static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin) -{ - struct samsung_gpio_chip *chip; - - if (pin > S3C_GPIO_END) - return NULL; - - chip = &s3c24xx_gpios[pin/32]; - return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL; -} - -#endif /* __ASM_ARCH_GPIO_CORE_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h deleted file mode 100644 index 6fac70f3484e..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/gpio.h +++ /dev/null @@ -1,35 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/gpio.h - * - * Copyright (c) 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - GPIO lib support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* some boards require extra gpio capacity to support external - * devices that need GPIO. - */ - -#ifdef CONFIG_CPU_S3C244X -#define ARCH_NR_GPIOS (32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA) -#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416) -#define ARCH_NR_GPIOS (32 * 12 + CONFIG_S3C24XX_GPIO_EXTRA) -#else -#define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA) -#endif - -#include <mach/gpio-nrs.h> -#include <mach/gpio-fns.h> - -#ifdef CONFIG_CPU_S3C244X -#define S3C_GPIO_END (S3C2410_GPJ(0) + 32) -#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416) -#define S3C_GPIO_END (S3C2410_GPM(0) + 32) -#else -#define S3C_GPIO_END (S3C2410_GPH(0) + 32) -#endif diff --git a/arch/arm/mach-s3c2410/include/mach/h1940-latch.h b/arch/arm/mach-s3c2410/include/mach/h1940-latch.h deleted file mode 100644 index fc897d3a056c..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/h1940-latch.h +++ /dev/null @@ -1,43 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/h1940-latch.h - * - * Copyright (c) 2005 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * iPAQ H1940 series - latch definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_H1940_LATCH_H -#define __ASM_ARCH_H1940_LATCH_H - -#include <asm/gpio.h> - -#define H1940_LATCH_GPIO(x) (S3C_GPIO_END + (x)) - -/* SD layer latch */ - -#define H1940_LATCH_LCD_P0 H1940_LATCH_GPIO(0) -#define H1940_LATCH_LCD_P1 H1940_LATCH_GPIO(1) -#define H1940_LATCH_LCD_P2 H1940_LATCH_GPIO(2) -#define H1940_LATCH_LCD_P3 H1940_LATCH_GPIO(3) -#define H1940_LATCH_MAX1698_nSHUTDOWN H1940_LATCH_GPIO(4) -#define H1940_LATCH_LED_RED H1940_LATCH_GPIO(5) -#define H1940_LATCH_SDQ7 H1940_LATCH_GPIO(6) -#define H1940_LATCH_USB_DP H1940_LATCH_GPIO(7) - -/* CPU layer latch */ - -#define H1940_LATCH_UDA_POWER H1940_LATCH_GPIO(8) -#define H1940_LATCH_AUDIO_POWER H1940_LATCH_GPIO(9) -#define H1940_LATCH_SM803_ENABLE H1940_LATCH_GPIO(10) -#define H1940_LATCH_LCD_P4 H1940_LATCH_GPIO(11) -#define H1940_LATCH_SD_POWER H1940_LATCH_GPIO(12) -#define H1940_LATCH_BLUETOOTH_POWER H1940_LATCH_GPIO(13) -#define H1940_LATCH_LED_GREEN H1940_LATCH_GPIO(14) -#define H1940_LATCH_LED_FLASH H1940_LATCH_GPIO(15) - -#endif /* __ASM_ARCH_H1940_LATCH_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/h1940.h b/arch/arm/mach-s3c2410/include/mach/h1940.h deleted file mode 100644 index 2aa683c8d3d6..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/h1940.h +++ /dev/null @@ -1,24 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/h1940.h - * - * Copyright 2006 Ben Dooks <ben-linux@fluff.org> - * - * H1940 definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_H1940_H -#define __ASM_ARCH_H1940_H - -#define H1940_SUSPEND_CHECKSUM (0x30003ff8) -#define H1940_SUSPEND_RESUMEAT (0x30081000) -#define H1940_SUSPEND_CHECK (0x30080000) - -extern void h1940_pm_return(void); -extern int h1940_led_blink_set(unsigned gpio, int state, - unsigned long *delay_on, unsigned long *delay_off); - - -#endif /* __ASM_ARCH_H1940_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/hardware.h b/arch/arm/mach-s3c2410/include/mach/hardware.h deleted file mode 100644 index aef5631eac58..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/hardware.h +++ /dev/null @@ -1,42 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/hardware.h - * - * Copyright (c) 2003 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - hardware - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#ifndef __ASSEMBLY__ - -extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg); - -#ifdef CONFIG_CPU_S3C2440 - -extern int s3c2440_set_dsc(unsigned int pin, unsigned int value); - -#endif /* CONFIG_CPU_S3C2440 */ - -#ifdef CONFIG_CPU_S3C2412 - -extern int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state); - -#endif /* CONFIG_CPU_S3C2412 */ - -#endif /* __ASSEMBLY__ */ - -#include <asm/sizes.h> -#include <mach/map.h> - -/* machine specific hardware definitions should go after this */ - -/* currently here until moved into config (todo) */ -#define CONFIG_NO_MULTIWORD_IO - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/idle.h b/arch/arm/mach-s3c2410/include/mach/idle.h deleted file mode 100644 index e9ddd706b16e..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/idle.h +++ /dev/null @@ -1,24 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/idle.h - * - * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 CPU Idle controls -*/ - -#ifndef __ASM_ARCH_IDLE_H -#define __ASM_ARCH_IDLE_H __FILE__ - -/* This allows the over-ride of the default idle code, in case there - * is any other things to be done over idle (like DVS) -*/ - -extern void (*s3c24xx_idle)(void); - -extern void s3c24xx_default_idle(void); - -#endif /* __ASM_ARCH_IDLE_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/io.h b/arch/arm/mach-s3c2410/include/mach/io.h deleted file mode 100644 index 118749f37c4c..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/io.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * arch/arm/mach-s3c2410/include/mach/io.h - * from arch/arm/mach-rpc/include/mach/io.h - * - * Copyright (C) 1997 Russell King - * (C) 2003 Simtec Electronics -*/ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#include <mach/hardware.h> - -#define IO_SPACE_LIMIT 0xffffffff - -/* - * We use two different types of addressing - PC style addresses, and ARM - * addresses. PC style accesses the PC hardware with the normal PC IO - * addresses, eg 0x3f8 for serial#1. ARM addresses are above A28 - * and are translated to the start of IO. Note that all addresses are - * not shifted left! - */ - -#define __PORT_PCIO(x) ((x) < (1<<28)) - -#define PCIO_BASE (S3C24XX_VA_ISA_WORD) -#define PCIO_BASE_b (S3C24XX_VA_ISA_BYTE) -#define PCIO_BASE_w (S3C24XX_VA_ISA_WORD) -#define PCIO_BASE_l (S3C24XX_VA_ISA_WORD) -/* - * Dynamic IO functions - let the compiler - * optimize the expressions - */ - -#define DECLARE_DYN_OUT(sz,fnsuffix,instr) \ -static inline void __out##fnsuffix (unsigned int val, unsigned int port) \ -{ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "cmp %2, #(1<<28)\n\t" \ - "mov %0, %2\n\t" \ - "addcc %0, %0, %3\n\t" \ - "str" instr " %1, [%0, #0 ] @ out" #fnsuffix \ - : "=&r" (temp) \ - : "r" (val), "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \ - : "cc"); \ -} - - -#define DECLARE_DYN_IN(sz,fnsuffix,instr) \ -static inline unsigned sz __in##fnsuffix (unsigned int port) \ -{ \ - unsigned long temp, value; \ - __asm__ __volatile__( \ - "cmp %2, #(1<<28)\n\t" \ - "mov %0, %2\n\t" \ - "addcc %0, %0, %3\n\t" \ - "ldr" instr " %1, [%0, #0 ] @ in" #fnsuffix \ - : "=&r" (temp), "=r" (value) \ - : "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \ - : "cc"); \ - return (unsigned sz)value; \ -} - -static inline void __iomem *__ioaddr (unsigned long port) -{ - return __PORT_PCIO(port) ? (PCIO_BASE + port) : (void __iomem *)port; -} - -#define DECLARE_IO(sz,fnsuffix,instr) \ - DECLARE_DYN_IN(sz,fnsuffix,instr) \ - DECLARE_DYN_OUT(sz,fnsuffix,instr) - -DECLARE_IO(char,b,"b") -DECLARE_IO(short,w,"h") -DECLARE_IO(int,l,"") - -#undef DECLARE_IO -#undef DECLARE_DYN_IN - -/* - * Constant address IO functions - * - * These have to be macros for the 'J' constraint to work - - * +/-4096 immediate operand. - */ -#define __outbc(value,port) \ -({ \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "strb %0, [%1, %2] @ outbc" \ - : : "r" (value), "r" (PCIO_BASE), "Jr" ((port))); \ - else \ - __asm__ __volatile__( \ - "strb %0, [%1, #0] @ outbc" \ - : : "r" (value), "r" ((port))); \ -}) - -#define __inbc(port) \ -({ \ - unsigned char result; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "ldrb %0, [%1, %2] @ inbc" \ - : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \ - else \ - __asm__ __volatile__( \ - "ldrb %0, [%1, #0] @ inbc" \ - : "=r" (result) : "r" ((port))); \ - result; \ -}) - -#define __outwc(value,port) \ -({ \ - unsigned long v = value; \ - if (__PORT_PCIO((port))) { \ - if ((port) < 256 && (port) > -256) \ - __asm__ __volatile__( \ - "strh %0, [%1, %2] @ outwc" \ - : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \ - else if ((port) > 0) \ - __asm__ __volatile__( \ - "strh %0, [%1, %2] @ outwc" \ - : : "r" (v), \ - "r" (PCIO_BASE + ((port) & ~0xff)), \ - "Jr" (((port) & 0xff))); \ - else \ - __asm__ __volatile__( \ - "strh %0, [%1, #0] @ outwc" \ - : : "r" (v), \ - "r" (PCIO_BASE + (port))); \ - } else \ - __asm__ __volatile__( \ - "strh %0, [%1, #0] @ outwc" \ - : : "r" (v), "r" ((port))); \ -}) - -#define __inwc(port) \ -({ \ - unsigned short result; \ - if (__PORT_PCIO((port))) { \ - if ((port) < 256 && (port) > -256 ) \ - __asm__ __volatile__( \ - "ldrh %0, [%1, %2] @ inwc" \ - : "=r" (result) \ - : "r" (PCIO_BASE), \ - "Jr" ((port))); \ - else if ((port) > 0) \ - __asm__ __volatile__( \ - "ldrh %0, [%1, %2] @ inwc" \ - : "=r" (result) \ - : "r" (PCIO_BASE + ((port) & ~0xff)), \ - "Jr" (((port) & 0xff))); \ - else \ - __asm__ __volatile__( \ - "ldrh %0, [%1, #0] @ inwc" \ - : "=r" (result) \ - : "r" (PCIO_BASE + ((port)))); \ - } else \ - __asm__ __volatile__( \ - "ldrh %0, [%1, #0] @ inwc" \ - : "=r" (result) : "r" ((port))); \ - result; \ -}) - -#define __outlc(value,port) \ -({ \ - unsigned long v = value; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "str %0, [%1, %2] @ outlc" \ - : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \ - else \ - __asm__ __volatile__( \ - "str %0, [%1, #0] @ outlc" \ - : : "r" (v), "r" ((port))); \ -}) - -#define __inlc(port) \ -({ \ - unsigned long result; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "ldr %0, [%1, %2] @ inlc" \ - : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \ - else \ - __asm__ __volatile__( \ - "ldr %0, [%1, #0] @ inlc" \ - : "=r" (result) : "r" ((port))); \ - result; \ -}) - -#define __ioaddrc(port) ((__PORT_PCIO(port) ? PCIO_BASE + (port) : (void __iomem *)(port))) - -#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p)) -#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p)) -#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p)) -#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p)) -#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p)) -#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p)) -#define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p)) - -#define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l) -#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l) -#define insl(p,d,l) __raw_readsl(__ioaddr(p),d,l) - -#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l) -#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l) -#define outsl(p,d,l) __raw_writesl(__ioaddr(p),d,l) - -/* - * 1:1 mapping for ioremapped regions. - */ -#define __mem_pci(x) (x) - -#endif diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h deleted file mode 100644 index e53b2177319e..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/irqs.h +++ /dev/null @@ -1,202 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/irqs.h - * - * Copyright (c) 2003-2005 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H __FILE__ - -/* we keep the first set of CPU IRQs out of the range of - * the ISA space, so that the PC104 has them to itself - * and we don't end up having to do horrible things to the - * standard ISA drivers.... - */ - -#define S3C2410_CPUIRQ_OFFSET (16) - -#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET) - -/* main cpu interrupts */ -#define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */ -#define IRQ_EINT1 S3C2410_IRQ(1) -#define IRQ_EINT2 S3C2410_IRQ(2) -#define IRQ_EINT3 S3C2410_IRQ(3) -#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */ -#define IRQ_EINT8t23 S3C2410_IRQ(5) -#define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */ -#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */ -#define IRQ_BATT_FLT S3C2410_IRQ(7) -#define IRQ_TICK S3C2410_IRQ(8) /* 24 */ -#define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */ -#define IRQ_TIMER0 S3C2410_IRQ(10) -#define IRQ_TIMER1 S3C2410_IRQ(11) -#define IRQ_TIMER2 S3C2410_IRQ(12) -#define IRQ_TIMER3 S3C2410_IRQ(13) -#define IRQ_TIMER4 S3C2410_IRQ(14) -#define IRQ_UART2 S3C2410_IRQ(15) -#define IRQ_LCD S3C2410_IRQ(16) /* 32 */ -#define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */ -#define IRQ_DMA1 S3C2410_IRQ(18) -#define IRQ_DMA2 S3C2410_IRQ(19) -#define IRQ_DMA3 S3C2410_IRQ(20) -#define IRQ_SDI S3C2410_IRQ(21) -#define IRQ_SPI0 S3C2410_IRQ(22) -#define IRQ_UART1 S3C2410_IRQ(23) -#define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */ -#define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */ -#define IRQ_USBD S3C2410_IRQ(25) -#define IRQ_USBH S3C2410_IRQ(26) -#define IRQ_IIC S3C2410_IRQ(27) -#define IRQ_UART0 S3C2410_IRQ(28) /* 44 */ -#define IRQ_SPI1 S3C2410_IRQ(29) -#define IRQ_RTC S3C2410_IRQ(30) -#define IRQ_ADCPARENT S3C2410_IRQ(31) - -/* interrupts generated from the external interrupts sources */ -#define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */ -#define IRQ_EINT5 S3C2410_IRQ(33) -#define IRQ_EINT6 S3C2410_IRQ(34) -#define IRQ_EINT7 S3C2410_IRQ(35) -#define IRQ_EINT8 S3C2410_IRQ(36) -#define IRQ_EINT9 S3C2410_IRQ(37) -#define IRQ_EINT10 S3C2410_IRQ(38) -#define IRQ_EINT11 S3C2410_IRQ(39) -#define IRQ_EINT12 S3C2410_IRQ(40) -#define IRQ_EINT13 S3C2410_IRQ(41) -#define IRQ_EINT14 S3C2410_IRQ(42) -#define IRQ_EINT15 S3C2410_IRQ(43) -#define IRQ_EINT16 S3C2410_IRQ(44) -#define IRQ_EINT17 S3C2410_IRQ(45) -#define IRQ_EINT18 S3C2410_IRQ(46) -#define IRQ_EINT19 S3C2410_IRQ(47) -#define IRQ_EINT20 S3C2410_IRQ(48) /* 64 */ -#define IRQ_EINT21 S3C2410_IRQ(49) -#define IRQ_EINT22 S3C2410_IRQ(50) -#define IRQ_EINT23 S3C2410_IRQ(51) - -#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4) -#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) - -#define IRQ_LCD_FIFO S3C2410_IRQ(52) -#define IRQ_LCD_FRAME S3C2410_IRQ(53) - -/* IRQs for the interal UARTs, and ADC - * these need to be ordered in number of appearance in the - * SUBSRC mask register -*/ - -#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+54) - -#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 70 */ -#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1) -#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2) - -#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 73 */ -#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4) -#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5) - -#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 76 */ -#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7) -#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8) - -#define IRQ_TC S3C2410_IRQSUB(9) -#define IRQ_ADC S3C2410_IRQSUB(10) - -/* extra irqs for s3c2412 */ - -#define IRQ_S3C2412_CFSDI S3C2410_IRQ(21) - -#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13) -#define IRQ_S3C2412_CF S3C2410_IRQSUB(14) - - -#define IRQ_S3C2416_EINT8t15 S3C2410_IRQ(5) -#define IRQ_S3C2416_DMA S3C2410_IRQ(17) -#define IRQ_S3C2416_UART3 S3C2410_IRQ(18) -#define IRQ_S3C2416_SDI1 S3C2410_IRQ(20) -#define IRQ_S3C2416_SDI0 S3C2410_IRQ(21) - -#define IRQ_S3C2416_LCD2 S3C2410_IRQSUB(15) -#define IRQ_S3C2416_LCD3 S3C2410_IRQSUB(16) -#define IRQ_S3C2416_LCD4 S3C2410_IRQSUB(17) -#define IRQ_S3C2416_DMA0 S3C2410_IRQSUB(18) -#define IRQ_S3C2416_DMA1 S3C2410_IRQSUB(19) -#define IRQ_S3C2416_DMA2 S3C2410_IRQSUB(20) -#define IRQ_S3C2416_DMA3 S3C2410_IRQSUB(21) -#define IRQ_S3C2416_DMA4 S3C2410_IRQSUB(22) -#define IRQ_S3C2416_DMA5 S3C2410_IRQSUB(23) -#define IRQ_S32416_WDT S3C2410_IRQSUB(27) -#define IRQ_S32416_AC97 S3C2410_IRQSUB(28) - - -/* extra irqs for s3c2440 */ - -#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */ -#define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */ -#define IRQ_S3C2440_WDT S3C2410_IRQSUB(13) -#define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14) - -/* irqs for s3c2443 */ - -#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */ -#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */ -#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */ -#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ -#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ - -#define IRQ_S3C2416_HSMMC0 S3C2410_IRQ(21) /* S3C2416/S3C2450 */ - -#define IRQ_HSMMC0 IRQ_S3C2416_HSMMC0 -#define IRQ_HSMMC1 IRQ_S3C2443_HSMMC - -#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) -#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) -#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16) -#define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17) - -#define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18) -#define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19) -#define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20) -#define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21) -#define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22) -#define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23) - -/* UART3 */ -#define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24) -#define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25) -#define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26) - -#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27) -#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28) - -#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416) -#define NR_IRQS (IRQ_S3C2443_AC97+1) -#else -#define NR_IRQS (IRQ_S3C2440_AC97+1) -#endif - -/* compatibility define. */ -#define IRQ_UART3 IRQ_S3C2443_UART3 -#define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3 -#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 -#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 - -#define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3 -#define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2 - -#ifdef CONFIG_CPU_S3C2440 -#define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97 -#else -#define IRQ_S3C244X_AC97 IRQ_S3C2443_AC97 -#endif - -/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ -#define FIQ_START IRQ_EINT0 - -#endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/leds-gpio.h b/arch/arm/mach-s3c2410/include/mach/leds-gpio.h deleted file mode 100644 index d8a7672519b6..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/leds-gpio.h +++ /dev/null @@ -1,28 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/leds-gpio.h - * - * Copyright (c) 2006 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C24XX - LEDs GPIO connector - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_LEDSGPIO_H -#define __ASM_ARCH_LEDSGPIO_H "leds-gpio.h" - -#define S3C24XX_LEDF_ACTLOW (1<<0) /* LED is on when GPIO low */ -#define S3C24XX_LEDF_TRISTATE (1<<1) /* tristate to turn off */ - -struct s3c24xx_led_platdata { - unsigned int gpio; - unsigned int flags; - - char *name; - char *def_trigger; -}; - -#endif /* __ASM_ARCH_LEDSGPIO_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h deleted file mode 100644 index 78ae807f1281..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/map.h +++ /dev/null @@ -1,165 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/map.h - * - * Copyright (c) 2003 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - Memory map definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_MAP_H -#define __ASM_ARCH_MAP_H - -#include <plat/map-base.h> - -/* - * S3C2410 UART offset is 0x4000 but the other SoCs are 0x400. - * So need to define it, and here is to avoid redefinition warning. - */ -#define S3C_UART_OFFSET (0x4000) - -#include <plat/map-s3c.h> - -/* - * interrupt controller is the first thing we put in, to make - * the assembly code for the irq detection easier - */ -#define S3C2410_PA_IRQ (0x4A000000) -#define S3C24XX_SZ_IRQ SZ_1M - -/* memory controller registers */ -#define S3C2410_PA_MEMCTRL (0x48000000) -#define S3C24XX_SZ_MEMCTRL SZ_1M - -/* UARTs */ -#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET))) - -/* Timers */ -#define S3C2410_PA_TIMER (0x51000000) -#define S3C24XX_SZ_TIMER SZ_1M - -/* Clock and Power management */ -#define S3C24XX_SZ_CLKPWR SZ_1M - -/* USB Device port */ -#define S3C2410_PA_USBDEV (0x52000000) -#define S3C24XX_SZ_USBDEV SZ_1M - -/* Watchdog */ -#define S3C2410_PA_WATCHDOG (0x53000000) -#define S3C24XX_SZ_WATCHDOG SZ_1M - -/* Standard size definitions for peripheral blocks. */ - -#define S3C24XX_SZ_UART SZ_1M -#define S3C24XX_SZ_IIS SZ_1M -#define S3C24XX_SZ_ADC SZ_1M -#define S3C24XX_SZ_SPI SZ_1M -#define S3C24XX_SZ_SDI SZ_1M -#define S3C24XX_SZ_NAND SZ_1M -#define S3C24XX_SZ_GPIO SZ_1M - -/* USB host controller */ -#define S3C2410_PA_USBHOST (0x49000000) - -/* S3C2416/S3C2443/S3C2450 High-Speed USB Gadget */ -#define S3C2416_PA_HSUDC (0x49800000) -#define S3C2416_SZ_HSUDC (SZ_4K) - -/* DMA controller */ -#define S3C2410_PA_DMA (0x4B000000) -#define S3C24XX_SZ_DMA SZ_1M - -/* Clock and Power management */ -#define S3C2410_PA_CLKPWR (0x4C000000) - -/* LCD controller */ -#define S3C2410_PA_LCD (0x4D000000) -#define S3C24XX_SZ_LCD SZ_1M - -/* NAND flash controller */ -#define S3C2410_PA_NAND (0x4E000000) - -/* IIC hardware controller */ -#define S3C2410_PA_IIC (0x54000000) - -/* IIS controller */ -#define S3C2410_PA_IIS (0x55000000) - -/* RTC */ -#define S3C2410_PA_RTC (0x57000000) -#define S3C24XX_SZ_RTC SZ_1M - -/* ADC */ -#define S3C2410_PA_ADC (0x58000000) - -/* SPI */ -#define S3C2410_PA_SPI (0x59000000) - -/* SDI */ -#define S3C2410_PA_SDI (0x5A000000) - -/* CAMIF */ -#define S3C2440_PA_CAMIF (0x4F000000) -#define S3C2440_SZ_CAMIF SZ_1M - -/* AC97 */ - -#define S3C2440_PA_AC97 (0x5B000000) -#define S3C2440_SZ_AC97 SZ_1M - -/* S3C2443/S3C2416 High-speed SD/MMC */ -#define S3C2443_PA_HSMMC (0x4A800000) -#define S3C2416_PA_HSMMC0 (0x4AC00000) - -#define S3C2443_PA_FB (0x4C800000) - -/* S3C2412 memory and IO controls */ -#define S3C2412_PA_SSMC (0x4F000000) - -#define S3C2412_PA_EBI (0x48800000) - -/* physical addresses of all the chip-select areas */ - -#define S3C2410_CS0 (0x00000000) -#define S3C2410_CS1 (0x08000000) -#define S3C2410_CS2 (0x10000000) -#define S3C2410_CS3 (0x18000000) -#define S3C2410_CS4 (0x20000000) -#define S3C2410_CS5 (0x28000000) -#define S3C2410_CS6 (0x30000000) -#define S3C2410_CS7 (0x38000000) - -#define S3C2410_SDRAM_PA (S3C2410_CS6) - -/* Use a single interface for common resources between S3C24XX cpus */ - -#define S3C24XX_PA_IRQ S3C2410_PA_IRQ -#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL -#define S3C24XX_PA_DMA S3C2410_PA_DMA -#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR -#define S3C24XX_PA_LCD S3C2410_PA_LCD -#define S3C24XX_PA_TIMER S3C2410_PA_TIMER -#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV -#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG -#define S3C24XX_PA_IIS S3C2410_PA_IIS -#define S3C24XX_PA_RTC S3C2410_PA_RTC -#define S3C24XX_PA_ADC S3C2410_PA_ADC -#define S3C24XX_PA_SPI S3C2410_PA_SPI -#define S3C24XX_PA_SPI1 (S3C2410_PA_SPI + S3C2410_SPI1) -#define S3C24XX_PA_SDI S3C2410_PA_SDI -#define S3C24XX_PA_NAND S3C2410_PA_NAND - -#define S3C_PA_FB S3C2443_PA_FB -#define S3C_PA_IIC S3C2410_PA_IIC -#define S3C_PA_UART S3C24XX_PA_UART -#define S3C_PA_USBHOST S3C2410_PA_USBHOST -#define S3C_PA_HSMMC0 S3C2416_PA_HSMMC0 -#define S3C_PA_HSMMC1 S3C2443_PA_HSMMC -#define S3C_PA_WDT S3C2410_PA_WATCHDOG -#define S3C_PA_NAND S3C24XX_PA_NAND - -#endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/osiris-cpld.h b/arch/arm/mach-s3c2410/include/mach/osiris-cpld.h deleted file mode 100644 index e9e36b0abbac..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/osiris-cpld.h +++ /dev/null @@ -1,30 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/osiris-cpld.h - * - * Copyright 2005 Simtec Electronics - * http://www.simtec.co.uk/products/ - * Ben Dooks <ben@simtec.co.uk> - * - * OSIRIS - CPLD control constants - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_OSIRISCPLD_H -#define __ASM_ARCH_OSIRISCPLD_H - -/* CTRL0 - NAND WP control */ - -#define OSIRIS_CTRL0_NANDSEL (0x3) -#define OSIRIS_CTRL0_BOOT_INT (1<<3) -#define OSIRIS_CTRL0_PCMCIA (1<<4) -#define OSIRIS_CTRL0_FIX8 (1<<5) -#define OSIRIS_CTRL0_PCMCIA_nWAIT (1<<6) -#define OSIRIS_CTRL0_PCMCIA_nIOIS16 (1<<7) - -#define OSIRIS_CTRL1_FIX8 (1<<0) - -#define OSIRIS_ID_REVMASK (0x7) - -#endif /* __ASM_ARCH_OSIRISCPLD_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/osiris-map.h b/arch/arm/mach-s3c2410/include/mach/osiris-map.h deleted file mode 100644 index 17380f848428..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/osiris-map.h +++ /dev/null @@ -1,42 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/osiris-map.h - * - * Copyright 2005 Simtec Electronics - * http://www.simtec.co.uk/products/ - * Ben Dooks <ben@simtec.co.uk> - * - * OSIRIS - Memory map definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* needs arch/map.h including with this */ - -#ifndef __ASM_ARCH_OSIRISMAP_H -#define __ASM_ARCH_OSIRISMAP_H - -/* start peripherals off after the S3C2410 */ - -#define OSIRIS_IOADDR(x) (S3C2410_ADDR((x) + 0x04000000)) - -#define OSIRIS_PA_CPLD (S3C2410_CS1 | (1<<26)) - -/* we put the CPLD registers next, to get them out of the way */ - -#define OSIRIS_VA_CTRL0 OSIRIS_IOADDR(0x00000000) -#define OSIRIS_PA_CTRL0 (OSIRIS_PA_CPLD) - -#define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00100000) -#define OSIRIS_PA_CTRL1 (OSIRIS_PA_CPLD + (1<<23)) - -#define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00200000) -#define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (2<<23)) - -#define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00300000) -#define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<23)) - -#define OSIRIS_VA_IDREG OSIRIS_IOADDR(0x00700000) -#define OSIRIS_PA_IDREG (OSIRIS_PA_CPLD + (7<<23)) - -#endif /* __ASM_ARCH_OSIRISMAP_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/otom-map.h b/arch/arm/mach-s3c2410/include/mach/otom-map.h deleted file mode 100644 index f9277a52c145..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/otom-map.h +++ /dev/null @@ -1,30 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/otom-map.h - * - * (c) 2005 Guillaume GOURAT / NexVision - * guillaume.gourat@nexvision.fr - * - * NexVision OTOM board memory map definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* needs arch/map.h including with this */ - -/* ok, we've used up to 0x01300000, now we need to find space for the - * peripherals that live in the nGCS[x] areas, which are quite numerous - * in their space. - */ - -#ifndef __ASM_ARCH_OTOMMAP_H -#define __ASM_ARCH_OTOMMAP_H - -#define OTOM_PA_CS8900A_BASE (S3C2410_CS3 + 0x01000000) /* nGCS3 +0x01000000 */ -#define OTOM_VA_CS8900A_BASE S3C2410_ADDR(0x04000000) /* 0xF4000000 */ - -/* physical offset addresses for the peripherals */ - -#define OTOM_PA_FLASH0_BASE (S3C2410_CS0) /* Bank 0 */ - -#endif /* __ASM_ARCH_OTOMMAP_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/pm-core.h b/arch/arm/mach-s3c2410/include/mach/pm-core.h deleted file mode 100644 index 2eef7e6f7675..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/pm-core.h +++ /dev/null @@ -1,67 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/include/pm-core.h - * - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C24xx - PM core support for arch/arm/plat-s3c/pm.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -static inline void s3c_pm_debug_init_uart(void) -{ - unsigned long tmp = __raw_readl(S3C2410_CLKCON); - - /* re-start uart clocks */ - tmp |= S3C2410_CLKCON_UART0; - tmp |= S3C2410_CLKCON_UART1; - tmp |= S3C2410_CLKCON_UART2; - - __raw_writel(tmp, S3C2410_CLKCON); - udelay(10); -} - -static inline void s3c_pm_arch_prepare_irqs(void) -{ - __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK); - __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK); - - /* ack any outstanding external interrupts before we go to sleep */ - - __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); - __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); - __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); - -} - -static inline void s3c_pm_arch_stop_clocks(void) -{ - __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */ -} - -static void s3c_pm_show_resume_irqs(int start, unsigned long which, - unsigned long mask); - -static inline void s3c_pm_arch_show_resume_irqs(void) -{ - S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n", - __raw_readl(S3C2410_SRCPND), - __raw_readl(S3C2410_EINTPEND)); - - s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND), - s3c_irqwake_intmask); - - s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND), - s3c_irqwake_eintmask); -} - -static inline void s3c_pm_arch_update_uart(void __iomem *regs, - struct pm_uart_save *save) -{ -} - -static inline void s3c_pm_restored_gpios(void) { } -static inline void samsung_pm_saved_gpios(void) { } diff --git a/arch/arm/mach-s3c2410/include/mach/regs-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-clock.h deleted file mode 100644 index 3415b60082d7..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-clock.h +++ /dev/null @@ -1,166 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-clock.h - * - * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 clock register definitions -*/ - -#ifndef __ASM_ARM_REGS_CLOCK -#define __ASM_ARM_REGS_CLOCK - -#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR) - -#define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s))) - -#define S3C2410_LOCKTIME S3C2410_CLKREG(0x00) -#define S3C2410_MPLLCON S3C2410_CLKREG(0x04) -#define S3C2410_UPLLCON S3C2410_CLKREG(0x08) -#define S3C2410_CLKCON S3C2410_CLKREG(0x0C) -#define S3C2410_CLKSLOW S3C2410_CLKREG(0x10) -#define S3C2410_CLKDIVN S3C2410_CLKREG(0x14) - -#define S3C2410_CLKCON_IDLE (1<<2) -#define S3C2410_CLKCON_POWER (1<<3) -#define S3C2410_CLKCON_NAND (1<<4) -#define S3C2410_CLKCON_LCDC (1<<5) -#define S3C2410_CLKCON_USBH (1<<6) -#define S3C2410_CLKCON_USBD (1<<7) -#define S3C2410_CLKCON_PWMT (1<<8) -#define S3C2410_CLKCON_SDI (1<<9) -#define S3C2410_CLKCON_UART0 (1<<10) -#define S3C2410_CLKCON_UART1 (1<<11) -#define S3C2410_CLKCON_UART2 (1<<12) -#define S3C2410_CLKCON_GPIO (1<<13) -#define S3C2410_CLKCON_RTC (1<<14) -#define S3C2410_CLKCON_ADC (1<<15) -#define S3C2410_CLKCON_IIC (1<<16) -#define S3C2410_CLKCON_IIS (1<<17) -#define S3C2410_CLKCON_SPI (1<<18) - -/* DCLKCON register addresses in gpio.h */ - -#define S3C2410_DCLKCON_DCLK0EN (1<<0) -#define S3C2410_DCLKCON_DCLK0_PCLK (0<<1) -#define S3C2410_DCLKCON_DCLK0_UCLK (1<<1) -#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4) -#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8) -#define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4) -#define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8) - -#define S3C2410_DCLKCON_DCLK1EN (1<<16) -#define S3C2410_DCLKCON_DCLK1_PCLK (0<<17) -#define S3C2410_DCLKCON_DCLK1_UCLK (1<<17) -#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20) -#define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24) -#define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20) -#define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24) - -#define S3C2410_CLKDIVN_PDIVN (1<<0) -#define S3C2410_CLKDIVN_HDIVN (1<<1) - -#define S3C2410_CLKSLOW_UCLK_OFF (1<<7) -#define S3C2410_CLKSLOW_MPLL_OFF (1<<5) -#define S3C2410_CLKSLOW_SLOW (1<<4) -#define S3C2410_CLKSLOW_SLOWVAL(x) (x) -#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7) - -#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) - -/* extra registers */ -#define S3C2440_CAMDIVN S3C2410_CLKREG(0x18) - -#define S3C2440_CLKCON_CAMERA (1<<19) -#define S3C2440_CLKCON_AC97 (1<<20) - -#define S3C2440_CLKDIVN_PDIVN (1<<0) -#define S3C2440_CLKDIVN_HDIVN_MASK (3<<1) -#define S3C2440_CLKDIVN_HDIVN_1 (0<<1) -#define S3C2440_CLKDIVN_HDIVN_2 (1<<1) -#define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1) -#define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1) -#define S3C2440_CLKDIVN_UCLK (1<<3) - -#define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0) -#define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4) -#define S3C2440_CAMDIVN_HCLK3_HALF (1<<8) -#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9) -#define S3C2440_CAMDIVN_DVSEN (1<<12) - -#define S3C2442_CAMDIVN_CAMCLK_DIV3 (1<<5) - -#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */ - -#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) - -#define S3C2412_OSCSET S3C2410_CLKREG(0x18) -#define S3C2412_CLKSRC S3C2410_CLKREG(0x1C) - -#define S3C2412_PLLCON_OFF (1<<20) - -#define S3C2412_CLKDIVN_PDIVN (1<<2) -#define S3C2412_CLKDIVN_HDIVN_MASK (3<<0) -#define S3C2412_CLKDIVN_ARMDIVN (1<<3) -#define S3C2412_CLKDIVN_DVSEN (1<<4) -#define S3C2412_CLKDIVN_HALFHCLK (1<<5) -#define S3C2412_CLKDIVN_USB48DIV (1<<6) -#define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8) -#define S3C2412_CLKDIVN_UARTDIV_SHIFT (8) -#define S3C2412_CLKDIVN_I2SDIV_MASK (15<<12) -#define S3C2412_CLKDIVN_I2SDIV_SHIFT (12) -#define S3C2412_CLKDIVN_CAMDIV_MASK (15<<16) -#define S3C2412_CLKDIVN_CAMDIV_SHIFT (16) - -#define S3C2412_CLKCON_WDT (1<<28) -#define S3C2412_CLKCON_SPI (1<<27) -#define S3C2412_CLKCON_IIS (1<<26) -#define S3C2412_CLKCON_IIC (1<<25) -#define S3C2412_CLKCON_ADC (1<<24) -#define S3C2412_CLKCON_RTC (1<<23) -#define S3C2412_CLKCON_GPIO (1<<22) -#define S3C2412_CLKCON_UART2 (1<<21) -#define S3C2412_CLKCON_UART1 (1<<20) -#define S3C2412_CLKCON_UART0 (1<<19) -#define S3C2412_CLKCON_SDI (1<<18) -#define S3C2412_CLKCON_PWMT (1<<17) -#define S3C2412_CLKCON_USBD (1<<16) -#define S3C2412_CLKCON_CAMCLK (1<<15) -#define S3C2412_CLKCON_UARTCLK (1<<14) -/* missing 13 */ -#define S3C2412_CLKCON_USB_HOST48 (1<<12) -#define S3C2412_CLKCON_USB_DEV48 (1<<11) -#define S3C2412_CLKCON_HCLKdiv2 (1<<10) -#define S3C2412_CLKCON_HCLKx2 (1<<9) -#define S3C2412_CLKCON_SDRAM (1<<8) -/* missing 7 */ -#define S3C2412_CLKCON_USBH S3C2410_CLKCON_USBH -#define S3C2412_CLKCON_LCDC S3C2410_CLKCON_LCDC -#define S3C2412_CLKCON_NAND S3C2410_CLKCON_NAND -#define S3C2412_CLKCON_DMA3 (1<<3) -#define S3C2412_CLKCON_DMA2 (1<<2) -#define S3C2412_CLKCON_DMA1 (1<<1) -#define S3C2412_CLKCON_DMA0 (1<<0) - -/* clock sourec controls */ - -#define S3C2412_CLKSRC_EXTCLKDIV_MASK (7 << 0) -#define S3C2412_CLKSRC_EXTCLKDIV_SHIFT (0) -#define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV (1<<3) -#define S3C2412_CLKSRC_MSYSCLK_MPLL (1<<4) -#define S3C2412_CLKSRC_USYSCLK_UPLL (1<<5) -#define S3C2412_CLKSRC_UARTCLK_MPLL (1<<8) -#define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9) -#define S3C2412_CLKSRC_USBCLK_HCLK (1<<10) -#define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11) -#define S3C2412_CLKSRC_UREFCLK_EXTCLK (1<<12) -#define S3C2412_CLKSRC_EREFCLK_EXTCLK (1<<14) - -#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */ - -#define S3C2416_CLKDIV2 S3C2410_CLKREG(0x28) - -#endif /* __ASM_ARM_REGS_CLOCK */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h b/arch/arm/mach-s3c2410/include/mach/regs-dsc.h deleted file mode 100644 index 98fd4a05587c..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h +++ /dev/null @@ -1,220 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-dsc.h - * - * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2440/S3C2412 Signal Drive Strength Control -*/ - - -#ifndef __ASM_ARCH_REGS_DSC_H -#define __ASM_ARCH_REGS_DSC_H "2440-dsc" - -#if defined(CONFIG_CPU_S3C2412) -#define S3C2412_DSC0 S3C2410_GPIOREG(0xdc) -#define S3C2412_DSC1 S3C2410_GPIOREG(0xe0) -#endif - -#if defined(CONFIG_CPU_S3C2416) -#define S3C2416_DSC0 S3C2410_GPIOREG(0xc0) -#define S3C2416_DSC1 S3C2410_GPIOREG(0xc4) -#define S3C2416_DSC2 S3C2410_GPIOREG(0xc8) -#define S3C2416_DSC3 S3C2410_GPIOREG(0x110) - -#define S3C2416_SELECT_DSC0 (0 << 30) -#define S3C2416_SELECT_DSC1 (1 << 30) -#define S3C2416_SELECT_DSC2 (2 << 30) -#define S3C2416_SELECT_DSC3 (3 << 30) - -#define S3C2416_DSC_GETSHIFT(x) (x & 30) - -#define S3C2416_DSC0_CF (S3C2416_SELECT_DSC0 | 28) -#define S3C2416_DSC0_CF_5mA (0 << 28) -#define S3C2416_DSC0_CF_10mA (1 << 28) -#define S3C2416_DSC0_CF_15mA (2 << 28) -#define S3C2416_DSC0_CF_21mA (3 << 28) -#define S3C2416_DSC0_CF_MASK (3 << 28) - -#define S3C2416_DSC0_nRBE (S3C2416_SELECT_DSC0 | 26) -#define S3C2416_DSC0_nRBE_5mA (0 << 26) -#define S3C2416_DSC0_nRBE_10mA (1 << 26) -#define S3C2416_DSC0_nRBE_15mA (2 << 26) -#define S3C2416_DSC0_nRBE_21mA (3 << 26) -#define S3C2416_DSC0_nRBE_MASK (3 << 26) - -#define S3C2416_DSC0_nROE (S3C2416_SELECT_DSC0 | 24) -#define S3C2416_DSC0_nROE_5mA (0 << 24) -#define S3C2416_DSC0_nROE_10mA (1 << 24) -#define S3C2416_DSC0_nROE_15mA (2 << 24) -#define S3C2416_DSC0_nROE_21mA (3 << 24) -#define S3C2416_DSC0_nROE_MASK (3 << 24) - -#endif - -#if defined(CONFIG_CPU_S3C244X) - -#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4) -#define S3C2440_DSC1 S3C2410_GPIOREG(0xc8) - -#define S3C2440_SELECT_DSC0 (0) -#define S3C2440_SELECT_DSC1 (1<<31) - -#define S3C2440_DSC_GETSHIFT(x) ((x) & 31) - -#define S3C2440_DSC0_DISABLE (1<<31) - -#define S3C2440_DSC0_ADDR (S3C2440_SELECT_DSC0 | 8) -#define S3C2440_DSC0_ADDR_12mA (0<<8) -#define S3C2440_DSC0_ADDR_10mA (1<<8) -#define S3C2440_DSC0_ADDR_8mA (2<<8) -#define S3C2440_DSC0_ADDR_6mA (3<<8) -#define S3C2440_DSC0_ADDR_MASK (3<<8) - -/* D24..D31 */ -#define S3C2440_DSC0_DATA3 (S3C2440_SELECT_DSC0 | 6) -#define S3C2440_DSC0_DATA3_12mA (0<<6) -#define S3C2440_DSC0_DATA3_10mA (1<<6) -#define S3C2440_DSC0_DATA3_8mA (2<<6) -#define S3C2440_DSC0_DATA3_6mA (3<<6) -#define S3C2440_DSC0_DATA3_MASK (3<<6) - -/* D16..D23 */ -#define S3C2440_DSC0_DATA2 (S3C2440_SELECT_DSC0 | 4) -#define S3C2440_DSC0_DATA2_12mA (0<<4) -#define S3C2440_DSC0_DATA2_10mA (1<<4) -#define S3C2440_DSC0_DATA2_8mA (2<<4) -#define S3C2440_DSC0_DATA2_6mA (3<<4) -#define S3C2440_DSC0_DATA2_MASK (3<<4) - -/* D8..D15 */ -#define S3C2440_DSC0_DATA1 (S3C2440_SELECT_DSC0 | 2) -#define S3C2440_DSC0_DATA1_12mA (0<<2) -#define S3C2440_DSC0_DATA1_10mA (1<<2) -#define S3C2440_DSC0_DATA1_8mA (2<<2) -#define S3C2440_DSC0_DATA1_6mA (3<<2) -#define S3C2440_DSC0_DATA1_MASK (3<<2) - -/* D0..D7 */ -#define S3C2440_DSC0_DATA0 (S3C2440_SELECT_DSC0 | 0) -#define S3C2440_DSC0_DATA0_12mA (0<<0) -#define S3C2440_DSC0_DATA0_10mA (1<<0) -#define S3C2440_DSC0_DATA0_8mA (2<<0) -#define S3C2440_DSC0_DATA0_6mA (3<<0) -#define S3C2440_DSC0_DATA0_MASK (3<<0) - -#define S3C2440_DSC1_SCK1 (S3C2440_SELECT_DSC1 | 28) -#define S3C2440_DSC1_SCK1_12mA (0<<28) -#define S3C2440_DSC1_SCK1_10mA (1<<28) -#define S3C2440_DSC1_SCK1_8mA (2<<28) -#define S3C2440_DSC1_SCK1_6mA (3<<28) -#define S3C2440_DSC1_SCK1_MASK (3<<28) - -#define S3C2440_DSC1_SCK0 (S3C2440_SELECT_DSC1 | 26) -#define S3C2440_DSC1_SCK0_12mA (0<<26) -#define S3C2440_DSC1_SCK0_10mA (1<<26) -#define S3C2440_DSC1_SCK0_8mA (2<<26) -#define S3C2440_DSC1_SCK0_6mA (3<<26) -#define S3C2440_DSC1_SCK0_MASK (3<<26) - -#define S3C2440_DSC1_SCKE (S3C2440_SELECT_DSC1 | 24) -#define S3C2440_DSC1_SCKE_10mA (0<<24) -#define S3C2440_DSC1_SCKE_8mA (1<<24) -#define S3C2440_DSC1_SCKE_6mA (2<<24) -#define S3C2440_DSC1_SCKE_4mA (3<<24) -#define S3C2440_DSC1_SCKE_MASK (3<<24) - -/* SDRAM nRAS/nCAS */ -#define S3C2440_DSC1_SDR (S3C2440_SELECT_DSC1 | 22) -#define S3C2440_DSC1_SDR_10mA (0<<22) -#define S3C2440_DSC1_SDR_8mA (1<<22) -#define S3C2440_DSC1_SDR_6mA (2<<22) -#define S3C2440_DSC1_SDR_4mA (3<<22) -#define S3C2440_DSC1_SDR_MASK (3<<22) - -/* NAND Flash Controller */ -#define S3C2440_DSC1_NFC (S3C2440_SELECT_DSC1 | 20) -#define S3C2440_DSC1_NFC_10mA (0<<20) -#define S3C2440_DSC1_NFC_8mA (1<<20) -#define S3C2440_DSC1_NFC_6mA (2<<20) -#define S3C2440_DSC1_NFC_4mA (3<<20) -#define S3C2440_DSC1_NFC_MASK (3<<20) - -/* nBE[0..3] */ -#define S3C2440_DSC1_nBE (S3C2440_SELECT_DSC1 | 18) -#define S3C2440_DSC1_nBE_10mA (0<<18) -#define S3C2440_DSC1_nBE_8mA (1<<18) -#define S3C2440_DSC1_nBE_6mA (2<<18) -#define S3C2440_DSC1_nBE_4mA (3<<18) -#define S3C2440_DSC1_nBE_MASK (3<<18) - -#define S3C2440_DSC1_WOE (S3C2440_SELECT_DSC1 | 16) -#define S3C2440_DSC1_WOE_10mA (0<<16) -#define S3C2440_DSC1_WOE_8mA (1<<16) -#define S3C2440_DSC1_WOE_6mA (2<<16) -#define S3C2440_DSC1_WOE_4mA (3<<16) -#define S3C2440_DSC1_WOE_MASK (3<<16) - -#define S3C2440_DSC1_CS7 (S3C2440_SELECT_DSC1 | 14) -#define S3C2440_DSC1_CS7_10mA (0<<14) -#define S3C2440_DSC1_CS7_8mA (1<<14) -#define S3C2440_DSC1_CS7_6mA (2<<14) -#define S3C2440_DSC1_CS7_4mA (3<<14) -#define S3C2440_DSC1_CS7_MASK (3<<14) - -#define S3C2440_DSC1_CS6 (S3C2440_SELECT_DSC1 | 12) -#define S3C2440_DSC1_CS6_10mA (0<<12) -#define S3C2440_DSC1_CS6_8mA (1<<12) -#define S3C2440_DSC1_CS6_6mA (2<<12) -#define S3C2440_DSC1_CS6_4mA (3<<12) -#define S3C2440_DSC1_CS6_MASK (3<<12) - -#define S3C2440_DSC1_CS5 (S3C2440_SELECT_DSC1 | 10) -#define S3C2440_DSC1_CS5_10mA (0<<10) -#define S3C2440_DSC1_CS5_8mA (1<<10) -#define S3C2440_DSC1_CS5_6mA (2<<10) -#define S3C2440_DSC1_CS5_4mA (3<<10) -#define S3C2440_DSC1_CS5_MASK (3<<10) - -#define S3C2440_DSC1_CS4 (S3C2440_SELECT_DSC1 | 8) -#define S3C2440_DSC1_CS4_10mA (0<<8) -#define S3C2440_DSC1_CS4_8mA (1<<8) -#define S3C2440_DSC1_CS4_6mA (2<<8) -#define S3C2440_DSC1_CS4_4mA (3<<8) -#define S3C2440_DSC1_CS4_MASK (3<<8) - -#define S3C2440_DSC1_CS3 (S3C2440_SELECT_DSC1 | 6) -#define S3C2440_DSC1_CS3_10mA (0<<6) -#define S3C2440_DSC1_CS3_8mA (1<<6) -#define S3C2440_DSC1_CS3_6mA (2<<6) -#define S3C2440_DSC1_CS3_4mA (3<<6) -#define S3C2440_DSC1_CS3_MASK (3<<6) - -#define S3C2440_DSC1_CS2 (S3C2440_SELECT_DSC1 | 4) -#define S3C2440_DSC1_CS2_10mA (0<<4) -#define S3C2440_DSC1_CS2_8mA (1<<4) -#define S3C2440_DSC1_CS2_6mA (2<<4) -#define S3C2440_DSC1_CS2_4mA (3<<4) -#define S3C2440_DSC1_CS2_MASK (3<<4) - -#define S3C2440_DSC1_CS1 (S3C2440_SELECT_DSC1 | 2) -#define S3C2440_DSC1_CS1_10mA (0<<2) -#define S3C2440_DSC1_CS1_8mA (1<<2) -#define S3C2440_DSC1_CS1_6mA (2<<2) -#define S3C2440_DSC1_CS1_4mA (3<<2) -#define S3C2440_DSC1_CS1_MASK (3<<2) - -#define S3C2440_DSC1_CS0 (S3C2440_SELECT_DSC1 | 0) -#define S3C2440_DSC1_CS0_10mA (0<<0) -#define S3C2440_DSC1_CS0_8mA (1<<0) -#define S3C2440_DSC1_CS0_6mA (2<<0) -#define S3C2440_DSC1_CS0_4mA (3<<0) -#define S3C2440_DSC1_CS0_MASK (3<<0) - -#endif /* CONFIG_CPU_S3C2440 */ - -#endif /* __ASM_ARCH_REGS_DSC_H */ - diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h deleted file mode 100644 index cac1ad6b582c..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ /dev/null @@ -1,602 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-gpio.h - * - * Copyright (c) 2003-2004 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 GPIO register definitions -*/ - - -#ifndef __ASM_ARCH_REGS_GPIO_H -#define __ASM_ARCH_REGS_GPIO_H - -#include <mach/gpio-nrs.h> - -#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) - -/* general configuration options */ - -#define S3C2410_GPIO_LEAVE (0xFFFFFFFF) -#define S3C2410_GPIO_INPUT (0xFFFFFFF0) /* not available on A */ -#define S3C2410_GPIO_OUTPUT (0xFFFFFFF1) -#define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */ -#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* bank A => addr/cs/nand */ -#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */ - -/* register address for the GPIO registers. - * S3C24XX_GPIOREG2 is for the second set of registers in the - * GPIO which move between s3c2410 and s3c2412 type systems */ - -#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO) -#define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2) - - -/* configure GPIO ports A..G */ - -/* port A - S3C2410: 22bits, zero in bit X makes pin X output - * 1 makes port special function, this is default -*/ -#define S3C2410_GPACON S3C2410_GPIOREG(0x00) -#define S3C2410_GPADAT S3C2410_GPIOREG(0x04) - -#define S3C2410_GPA0_ADDR0 (1<<0) -#define S3C2410_GPA1_ADDR16 (1<<1) -#define S3C2410_GPA2_ADDR17 (1<<2) -#define S3C2410_GPA3_ADDR18 (1<<3) -#define S3C2410_GPA4_ADDR19 (1<<4) -#define S3C2410_GPA5_ADDR20 (1<<5) -#define S3C2410_GPA6_ADDR21 (1<<6) -#define S3C2410_GPA7_ADDR22 (1<<7) -#define S3C2410_GPA8_ADDR23 (1<<8) -#define S3C2410_GPA9_ADDR24 (1<<9) -#define S3C2410_GPA10_ADDR25 (1<<10) -#define S3C2410_GPA11_ADDR26 (1<<11) -#define S3C2410_GPA12_nGCS1 (1<<12) -#define S3C2410_GPA13_nGCS2 (1<<13) -#define S3C2410_GPA14_nGCS3 (1<<14) -#define S3C2410_GPA15_nGCS4 (1<<15) -#define S3C2410_GPA16_nGCS5 (1<<16) -#define S3C2410_GPA17_CLE (1<<17) -#define S3C2410_GPA18_ALE (1<<18) -#define S3C2410_GPA19_nFWE (1<<19) -#define S3C2410_GPA20_nFRE (1<<20) -#define S3C2410_GPA21_nRSTOUT (1<<21) -#define S3C2410_GPA22_nFCE (1<<22) - -/* 0x08 and 0x0c are reserved on S3C2410 */ - -/* S3C2410: - * GPB is 10 IO pins, each configured by 2 bits each in GPBCON. - * 00 = input, 01 = output, 10=special function, 11=reserved - - * bit 0,1 = pin 0, 2,3= pin 1... - * - * CPBUP = pull up resistor control, 1=disabled, 0=enabled -*/ - -#define S3C2410_GPBCON S3C2410_GPIOREG(0x10) -#define S3C2410_GPBDAT S3C2410_GPIOREG(0x14) -#define S3C2410_GPBUP S3C2410_GPIOREG(0x18) - -/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ - -#define S3C2410_GPB0_TOUT0 (0x02 << 0) - -#define S3C2410_GPB1_TOUT1 (0x02 << 2) - -#define S3C2410_GPB2_TOUT2 (0x02 << 4) - -#define S3C2410_GPB3_TOUT3 (0x02 << 6) - -#define S3C2410_GPB4_TCLK0 (0x02 << 8) -#define S3C2410_GPB4_MASK (0x03 << 8) - -#define S3C2410_GPB5_nXBACK (0x02 << 10) -#define S3C2443_GPB5_XBACK (0x03 << 10) - -#define S3C2410_GPB6_nXBREQ (0x02 << 12) -#define S3C2443_GPB6_XBREQ (0x03 << 12) - -#define S3C2410_GPB7_nXDACK1 (0x02 << 14) -#define S3C2443_GPB7_XDACK1 (0x03 << 14) - -#define S3C2410_GPB8_nXDREQ1 (0x02 << 16) - -#define S3C2410_GPB9_nXDACK0 (0x02 << 18) -#define S3C2443_GPB9_XDACK0 (0x03 << 18) - -#define S3C2410_GPB10_nXDRE0 (0x02 << 20) -#define S3C2443_GPB10_XDREQ0 (0x03 << 20) - -#define S3C2410_GPB_PUPDIS(x) (1<<(x)) - -/* Port C consits of 16 GPIO/Special function - * - * almost identical setup to port b, but the special functions are mostly - * to do with the video system's sync/etc. -*/ - -#define S3C2410_GPCCON S3C2410_GPIOREG(0x20) -#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24) -#define S3C2410_GPCUP S3C2410_GPIOREG(0x28) -#define S3C2410_GPC0_LEND (0x02 << 0) -#define S3C2410_GPC1_VCLK (0x02 << 2) -#define S3C2410_GPC2_VLINE (0x02 << 4) -#define S3C2410_GPC3_VFRAME (0x02 << 6) -#define S3C2410_GPC4_VM (0x02 << 8) -#define S3C2410_GPC5_LCDVF0 (0x02 << 10) -#define S3C2410_GPC6_LCDVF1 (0x02 << 12) -#define S3C2410_GPC7_LCDVF2 (0x02 << 14) -#define S3C2410_GPC8_VD0 (0x02 << 16) -#define S3C2410_GPC9_VD1 (0x02 << 18) -#define S3C2410_GPC10_VD2 (0x02 << 20) -#define S3C2410_GPC11_VD3 (0x02 << 22) -#define S3C2410_GPC12_VD4 (0x02 << 24) -#define S3C2410_GPC13_VD5 (0x02 << 26) -#define S3C2410_GPC14_VD6 (0x02 << 28) -#define S3C2410_GPC15_VD7 (0x02 << 30) -#define S3C2410_GPC_PUPDIS(x) (1<<(x)) - -/* - * S3C2410: Port D consists of 16 GPIO/Special function - * - * almost identical setup to port b, but the special functions are mostly - * to do with the video system's data. - * - * almost identical setup to port c -*/ - -#define S3C2410_GPDCON S3C2410_GPIOREG(0x30) -#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34) -#define S3C2410_GPDUP S3C2410_GPIOREG(0x38) - -#define S3C2410_GPD0_VD8 (0x02 << 0) -#define S3C2442_GPD0_nSPICS1 (0x03 << 0) - -#define S3C2410_GPD1_VD9 (0x02 << 2) -#define S3C2442_GPD1_SPICLK1 (0x03 << 2) - -#define S3C2410_GPD2_VD10 (0x02 << 4) - -#define S3C2410_GPD3_VD11 (0x02 << 6) - -#define S3C2410_GPD4_VD12 (0x02 << 8) - -#define S3C2410_GPD5_VD13 (0x02 << 10) - -#define S3C2410_GPD6_VD14 (0x02 << 12) - -#define S3C2410_GPD7_VD15 (0x02 << 14) - -#define S3C2410_GPD8_VD16 (0x02 << 16) -#define S3C2440_GPD8_SPIMISO1 (0x03 << 16) - -#define S3C2410_GPD9_VD17 (0x02 << 18) -#define S3C2440_GPD9_SPIMOSI1 (0x03 << 18) - -#define S3C2410_GPD10_VD18 (0x02 << 20) -#define S3C2440_GPD10_SPICLK1 (0x03 << 20) - -#define S3C2410_GPD11_VD19 (0x02 << 22) - -#define S3C2410_GPD12_VD20 (0x02 << 24) - -#define S3C2410_GPD13_VD21 (0x02 << 26) - -#define S3C2410_GPD14_VD22 (0x02 << 28) -#define S3C2410_GPD14_nSS1 (0x03 << 28) - -#define S3C2410_GPD15_VD23 (0x02 << 30) -#define S3C2410_GPD15_nSS0 (0x03 << 30) - -#define S3C2410_GPD_PUPDIS(x) (1<<(x)) - -/* S3C2410: - * Port E consists of 16 GPIO/Special function - * - * again, the same as port B, but dealing with I2S, SDI, and - * more miscellaneous functions - * - * GPIO / interrupt inputs -*/ - -#define S3C2410_GPECON S3C2410_GPIOREG(0x40) -#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44) -#define S3C2410_GPEUP S3C2410_GPIOREG(0x48) - -#define S3C2410_GPE0_I2SLRCK (0x02 << 0) -#define S3C2443_GPE0_AC_nRESET (0x03 << 0) -#define S3C2410_GPE0_MASK (0x03 << 0) - -#define S3C2410_GPE1_I2SSCLK (0x02 << 2) -#define S3C2443_GPE1_AC_SYNC (0x03 << 2) -#define S3C2410_GPE1_MASK (0x03 << 2) - -#define S3C2410_GPE2_CDCLK (0x02 << 4) -#define S3C2443_GPE2_AC_BITCLK (0x03 << 4) - -#define S3C2410_GPE3_I2SSDI (0x02 << 6) -#define S3C2443_GPE3_AC_SDI (0x03 << 6) -#define S3C2410_GPE3_nSS0 (0x03 << 6) -#define S3C2410_GPE3_MASK (0x03 << 6) - -#define S3C2410_GPE4_I2SSDO (0x02 << 8) -#define S3C2443_GPE4_AC_SDO (0x03 << 8) -#define S3C2410_GPE4_I2SSDI (0x03 << 8) -#define S3C2410_GPE4_MASK (0x03 << 8) - -#define S3C2410_GPE5_SDCLK (0x02 << 10) -#define S3C2443_GPE5_SD1_CLK (0x02 << 10) -#define S3C2443_GPE5_AC_BITCLK (0x03 << 10) - -#define S3C2410_GPE6_SDCMD (0x02 << 12) -#define S3C2443_GPE6_SD1_CMD (0x02 << 12) -#define S3C2443_GPE6_AC_SDI (0x03 << 12) - -#define S3C2410_GPE7_SDDAT0 (0x02 << 14) -#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) -#define S3C2443_GPE7_AC_SDO (0x03 << 14) - -#define S3C2410_GPE8_SDDAT1 (0x02 << 16) -#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) -#define S3C2443_GPE8_AC_SYNC (0x03 << 16) - -#define S3C2410_GPE9_SDDAT2 (0x02 << 18) -#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) -#define S3C2443_GPE9_AC_nRESET (0x03 << 18) - -#define S3C2410_GPE10_SDDAT3 (0x02 << 20) -#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) - -#define S3C2410_GPE11_SPIMISO0 (0x02 << 22) - -#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) - -#define S3C2410_GPE13_SPICLK0 (0x02 << 26) - -#define S3C2410_GPE14_IICSCL (0x02 << 28) -#define S3C2410_GPE14_MASK (0x03 << 28) - -#define S3C2410_GPE15_IICSDA (0x02 << 30) -#define S3C2410_GPE15_MASK (0x03 << 30) - -#define S3C2440_GPE0_ACSYNC (0x03 << 0) -#define S3C2440_GPE1_ACBITCLK (0x03 << 2) -#define S3C2440_GPE2_ACRESET (0x03 << 4) -#define S3C2440_GPE3_ACIN (0x03 << 6) -#define S3C2440_GPE4_ACOUT (0x03 << 8) - -#define S3C2410_GPE_PUPDIS(x) (1<<(x)) - -/* S3C2410: - * Port F consists of 8 GPIO/Special function - * - * GPIO / interrupt inputs - * - * GPFCON has 2 bits for each of the input pins on port F - * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined - * - * pull up works like all other ports. - * - * GPIO/serial/misc pins -*/ - -#define S3C2410_GPFCON S3C2410_GPIOREG(0x50) -#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54) -#define S3C2410_GPFUP S3C2410_GPIOREG(0x58) - -#define S3C2410_GPF0_EINT0 (0x02 << 0) -#define S3C2410_GPF1_EINT1 (0x02 << 2) -#define S3C2410_GPF2_EINT2 (0x02 << 4) -#define S3C2410_GPF3_EINT3 (0x02 << 6) -#define S3C2410_GPF4_EINT4 (0x02 << 8) -#define S3C2410_GPF5_EINT5 (0x02 << 10) -#define S3C2410_GPF6_EINT6 (0x02 << 12) -#define S3C2410_GPF7_EINT7 (0x02 << 14) -#define S3C2410_GPF_PUPDIS(x) (1<<(x)) - -/* S3C2410: - * Port G consists of 8 GPIO/IRQ/Special function - * - * GPGCON has 2 bits for each of the input pins on port F - * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func - * - * pull up works like all other ports. -*/ - -#define S3C2410_GPGCON S3C2410_GPIOREG(0x60) -#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64) -#define S3C2410_GPGUP S3C2410_GPIOREG(0x68) - -#define S3C2410_GPG0_EINT8 (0x02 << 0) - -#define S3C2410_GPG1_EINT9 (0x02 << 2) - -#define S3C2410_GPG2_EINT10 (0x02 << 4) -#define S3C2410_GPG2_nSS0 (0x03 << 4) - -#define S3C2410_GPG3_EINT11 (0x02 << 6) -#define S3C2410_GPG3_nSS1 (0x03 << 6) - -#define S3C2410_GPG4_EINT12 (0x02 << 8) -#define S3C2410_GPG4_LCDPWREN (0x03 << 8) -#define S3C2443_GPG4_LCDPWRDN (0x03 << 8) - -#define S3C2410_GPG5_EINT13 (0x02 << 10) -#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ - -#define S3C2410_GPG6_EINT14 (0x02 << 12) -#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) - -#define S3C2410_GPG7_EINT15 (0x02 << 14) -#define S3C2410_GPG7_SPICLK1 (0x03 << 14) - -#define S3C2410_GPG8_EINT16 (0x02 << 16) - -#define S3C2410_GPG9_EINT17 (0x02 << 18) - -#define S3C2410_GPG10_EINT18 (0x02 << 20) - -#define S3C2410_GPG11_EINT19 (0x02 << 22) -#define S3C2410_GPG11_TCLK1 (0x03 << 22) -#define S3C2443_GPG11_CF_nIREQ (0x03 << 22) - -#define S3C2410_GPG12_EINT20 (0x02 << 24) -#define S3C2410_GPG12_XMON (0x03 << 24) -#define S3C2442_GPG12_nSPICS0 (0x03 << 24) -#define S3C2443_GPG12_nINPACK (0x03 << 24) - -#define S3C2410_GPG13_EINT21 (0x02 << 26) -#define S3C2410_GPG13_nXPON (0x03 << 26) -#define S3C2443_GPG13_CF_nREG (0x03 << 26) - -#define S3C2410_GPG14_EINT22 (0x02 << 28) -#define S3C2410_GPG14_YMON (0x03 << 28) -#define S3C2443_GPG14_CF_RESET (0x03 << 28) - -#define S3C2410_GPG15_EINT23 (0x02 << 30) -#define S3C2410_GPG15_nYPON (0x03 << 30) -#define S3C2443_GPG15_CF_PWR (0x03 << 30) - -#define S3C2410_GPG_PUPDIS(x) (1<<(x)) - -/* Port H consists of11 GPIO/serial/Misc pins - * - * GPGCON has 2 bits for each of the input pins on port F - * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func - * - * pull up works like all other ports. -*/ - -#define S3C2410_GPHCON S3C2410_GPIOREG(0x70) -#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74) -#define S3C2410_GPHUP S3C2410_GPIOREG(0x78) - -#define S3C2410_GPH0_nCTS0 (0x02 << 0) -#define S3C2416_GPH0_TXD0 (0x02 << 0) - -#define S3C2410_GPH1_nRTS0 (0x02 << 2) -#define S3C2416_GPH1_RXD0 (0x02 << 2) - -#define S3C2410_GPH2_TXD0 (0x02 << 4) -#define S3C2416_GPH2_TXD1 (0x02 << 4) - -#define S3C2410_GPH3_RXD0 (0x02 << 6) -#define S3C2416_GPH3_RXD1 (0x02 << 6) - -#define S3C2410_GPH4_TXD1 (0x02 << 8) -#define S3C2416_GPH4_TXD2 (0x02 << 8) - -#define S3C2410_GPH5_RXD1 (0x02 << 10) -#define S3C2416_GPH5_RXD2 (0x02 << 10) - -#define S3C2410_GPH6_TXD2 (0x02 << 12) -#define S3C2416_GPH6_TXD3 (0x02 << 12) -#define S3C2410_GPH6_nRTS1 (0x03 << 12) -#define S3C2416_GPH6_nRTS2 (0x03 << 12) - -#define S3C2410_GPH7_RXD2 (0x02 << 14) -#define S3C2416_GPH7_RXD3 (0x02 << 14) -#define S3C2410_GPH7_nCTS1 (0x03 << 14) -#define S3C2416_GPH7_nCTS2 (0x03 << 14) - -#define S3C2410_GPH8_UCLK (0x02 << 16) -#define S3C2416_GPH8_nCTS0 (0x02 << 16) - -#define S3C2410_GPH9_CLKOUT0 (0x02 << 18) -#define S3C2442_GPH9_nSPICS0 (0x03 << 18) -#define S3C2416_GPH9_nRTS0 (0x02 << 18) - -#define S3C2410_GPH10_CLKOUT1 (0x02 << 20) -#define S3C2416_GPH10_nCTS1 (0x02 << 20) - -#define S3C2416_GPH11_nRTS1 (0x02 << 22) - -#define S3C2416_GPH12_EXTUARTCLK (0x02 << 24) - -#define S3C2416_GPH13_CLKOUT0 (0x02 << 26) - -#define S3C2416_GPH14_CLKOUT1 (0x02 << 28) - -/* The S3C2412 and S3C2413 move the GPJ register set to after - * GPH, which means all registers after 0x80 are now offset by 0x10 - * for the 2412/2413 from the 2410/2440/2442 -*/ - -/* S3C2443 and above */ -#define S3C2440_GPJCON S3C2410_GPIOREG(0xD0) -#define S3C2440_GPJDAT S3C2410_GPIOREG(0xD4) -#define S3C2440_GPJUP S3C2410_GPIOREG(0xD8) - -#define S3C2443_GPKCON S3C2410_GPIOREG(0xE0) -#define S3C2443_GPKDAT S3C2410_GPIOREG(0xE4) -#define S3C2443_GPKUP S3C2410_GPIOREG(0xE8) - -#define S3C2443_GPLCON S3C2410_GPIOREG(0xF0) -#define S3C2443_GPLDAT S3C2410_GPIOREG(0xF4) -#define S3C2443_GPLUP S3C2410_GPIOREG(0xF8) - -#define S3C2443_GPMCON S3C2410_GPIOREG(0x100) -#define S3C2443_GPMDAT S3C2410_GPIOREG(0x104) -#define S3C2443_GPMUP S3C2410_GPIOREG(0x108) - -/* miscellaneous control */ -#define S3C2410_MISCCR S3C2410_GPIOREG(0x80) -#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84) - -#define S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84) - -/* see clock.h for dclk definitions */ - -/* pullup control on databus */ -#define S3C2410_MISCCR_SPUCR_HEN (0<<0) -#define S3C2410_MISCCR_SPUCR_HDIS (1<<0) -#define S3C2410_MISCCR_SPUCR_LEN (0<<1) -#define S3C2410_MISCCR_SPUCR_LDIS (1<<1) - -#define S3C2410_MISCCR_USBDEV (0<<3) -#define S3C2410_MISCCR_USBHOST (1<<3) - -#define S3C2410_MISCCR_CLK0_MPLL (0<<4) -#define S3C2410_MISCCR_CLK0_UPLL (1<<4) -#define S3C2410_MISCCR_CLK0_FCLK (2<<4) -#define S3C2410_MISCCR_CLK0_HCLK (3<<4) -#define S3C2410_MISCCR_CLK0_PCLK (4<<4) -#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4) -#define S3C2410_MISCCR_CLK0_MASK (7<<4) - -#define S3C2412_MISCCR_CLK0_RTC (2<<4) - -#define S3C2410_MISCCR_CLK1_MPLL (0<<8) -#define S3C2410_MISCCR_CLK1_UPLL (1<<8) -#define S3C2410_MISCCR_CLK1_FCLK (2<<8) -#define S3C2410_MISCCR_CLK1_HCLK (3<<8) -#define S3C2410_MISCCR_CLK1_PCLK (4<<8) -#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8) -#define S3C2410_MISCCR_CLK1_MASK (7<<8) - -#define S3C2412_MISCCR_CLK1_CLKsrc (0<<8) - -#define S3C2410_MISCCR_USBSUSPND0 (1<<12) -#define S3C2416_MISCCR_SEL_SUSPND (1<<12) -#define S3C2410_MISCCR_USBSUSPND1 (1<<13) - -#define S3C2410_MISCCR_nRSTCON (1<<16) - -#define S3C2410_MISCCR_nEN_SCLK0 (1<<17) -#define S3C2410_MISCCR_nEN_SCLK1 (1<<18) -#define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */ -#define S3C2410_MISCCR_SDSLEEP (7<<17) - -#define S3C2416_MISCCR_FLT_I2C (1<<24) -#define S3C2416_MISCCR_HSSPI_EN2 (1<<31) - -/* external interrupt control... */ -/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7 - * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15 - * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23 - * - * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23 - * - * Samsung datasheet p9-25 -*/ -#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88) -#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C) -#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90) - -#define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88) -#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C) -#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90) - -/* interrupt filtering conrrol for EINT16..EINT23 */ -#define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94) -#define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98) -#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C) -#define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0) - -#define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94) -#define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98) -#define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C) -#define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0) - -/* values for interrupt filtering */ -#define S3C2410_EINTFLT_PCLK (0x00) -#define S3C2410_EINTFLT_EXTCLK (1<<7) -#define S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f) - -/* removed EINTxxxx defs from here, not meant for this */ - -/* GSTATUS have miscellaneous information in them - * - * These move between s3c2410 and s3c2412 style systems. - */ - -#define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC) -#define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0) -#define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4) -#define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8) -#define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC) - -#define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC) -#define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0) -#define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4) -#define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8) -#define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC) - -#define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC) -#define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0) -#define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4) -#define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8) -#define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC) - -#define S3C2410_GSTATUS0_nWAIT (1<<3) -#define S3C2410_GSTATUS0_NCON (1<<2) -#define S3C2410_GSTATUS0_RnB (1<<1) -#define S3C2410_GSTATUS0_nBATTFLT (1<<0) - -#define S3C2410_GSTATUS1_IDMASK (0xffff0000) -#define S3C2410_GSTATUS1_2410 (0x32410000) -#define S3C2410_GSTATUS1_2412 (0x32412001) -#define S3C2410_GSTATUS1_2416 (0x32416003) -#define S3C2410_GSTATUS1_2440 (0x32440000) -#define S3C2410_GSTATUS1_2442 (0x32440aaa) -/* some 2416 CPUs report this value also */ -#define S3C2410_GSTATUS1_2450 (0x32450003) - -#define S3C2410_GSTATUS2_WTRESET (1<<2) -#define S3C2410_GSTATUS2_OFFRESET (1<<1) -#define S3C2410_GSTATUS2_PONRESET (1<<0) - -/* 2412/2413 sleep configuration registers */ - -#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C) -#define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C) -#define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C) -#define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C) -#define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C) -#define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C) - -/* definitions for each pin bit */ -#define S3C2412_GPIO_SLPCON_LOW ( 0x00 ) -#define S3C2412_GPIO_SLPCON_HIGH ( 0x01 ) -#define S3C2412_GPIO_SLPCON_IN ( 0x02 ) -#define S3C2412_GPIO_SLPCON_PULL ( 0x03 ) - -#define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2)) -#define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2)) -#define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2)) -#define S3C2412_SLPCON_PULL(x) ( 0x03 << ((x) * 2)) -#define S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */ -#define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2)) - -#define S3C2412_SLPCON_ALL_LOW (0x0) -#define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444) -#define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888) -#define S3C2412_SLPCON_ALL_PULL (0x33333333) - -#endif /* __ASM_ARCH_REGS_GPIO_H */ - diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h b/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h deleted file mode 100644 index 19575e061114..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h +++ /dev/null @@ -1,70 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-gpioj.h - * - * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2440 GPIO J register definitions -*/ - - -#ifndef __ASM_ARCH_REGS_GPIOJ_H -#define __ASM_ARCH_REGS_GPIOJ_H "gpioj" - -/* Port J consists of 13 GPIO/Camera pins - * - * GPJCON has 2 bits for each of the input pins on port F - * 00 = 0 input, 1 output, 2 Camera - * - * pull up works like all other ports. -*/ - -#define S3C2413_GPJCON S3C2410_GPIOREG(0x80) -#define S3C2413_GPJDAT S3C2410_GPIOREG(0x84) -#define S3C2413_GPJUP S3C2410_GPIOREG(0x88) -#define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C) - -#define S3C2440_GPJ0_OUTP (0x01 << 0) -#define S3C2440_GPJ0_CAMDATA0 (0x02 << 0) - -#define S3C2440_GPJ1_OUTP (0x01 << 2) -#define S3C2440_GPJ1_CAMDATA1 (0x02 << 2) - -#define S3C2440_GPJ2_OUTP (0x01 << 4) -#define S3C2440_GPJ2_CAMDATA2 (0x02 << 4) - -#define S3C2440_GPJ3_OUTP (0x01 << 6) -#define S3C2440_GPJ3_CAMDATA3 (0x02 << 6) - -#define S3C2440_GPJ4_OUTP (0x01 << 8) -#define S3C2440_GPJ4_CAMDATA4 (0x02 << 8) - -#define S3C2440_GPJ5_OUTP (0x01 << 10) -#define S3C2440_GPJ5_CAMDATA5 (0x02 << 10) - -#define S3C2440_GPJ6_OUTP (0x01 << 12) -#define S3C2440_GPJ6_CAMDATA6 (0x02 << 12) - -#define S3C2440_GPJ7_OUTP (0x01 << 14) -#define S3C2440_GPJ7_CAMDATA7 (0x02 << 14) - -#define S3C2440_GPJ8_OUTP (0x01 << 16) -#define S3C2440_GPJ8_CAMPCLK (0x02 << 16) - -#define S3C2440_GPJ9_OUTP (0x01 << 18) -#define S3C2440_GPJ9_CAMVSYNC (0x02 << 18) - -#define S3C2440_GPJ10_OUTP (0x01 << 20) -#define S3C2440_GPJ10_CAMHREF (0x02 << 20) - -#define S3C2440_GPJ11_OUTP (0x01 << 22) -#define S3C2440_GPJ11_CAMCLKOUT (0x02 << 22) - -#define S3C2440_GPJ12_OUTP (0x01 << 24) -#define S3C2440_GPJ12_CAMRESET (0x02 << 24) - -#endif /* __ASM_ARCH_REGS_GPIOJ_H */ - diff --git a/arch/arm/mach-s3c2410/include/mach/regs-irq.h b/arch/arm/mach-s3c2410/include/mach/regs-irq.h deleted file mode 100644 index 0f07ba30b1fb..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-irq.h +++ /dev/null @@ -1,53 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-irq.h - * - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - - -#ifndef ___ASM_ARCH_REGS_IRQ_H -#define ___ASM_ARCH_REGS_IRQ_H - -/* interrupt controller */ - -#define S3C2410_IRQREG(x) ((x) + S3C24XX_VA_IRQ) -#define S3C2410_EINTREG(x) ((x) + S3C24XX_VA_GPIO) -#define S3C24XX_EINTREG(x) ((x) + S3C24XX_VA_GPIO2) - -#define S3C2410_SRCPND S3C2410_IRQREG(0x000) -#define S3C2410_INTMOD S3C2410_IRQREG(0x004) -#define S3C2410_INTMSK S3C2410_IRQREG(0x008) -#define S3C2410_PRIORITY S3C2410_IRQREG(0x00C) -#define S3C2410_INTPND S3C2410_IRQREG(0x010) -#define S3C2410_INTOFFSET S3C2410_IRQREG(0x014) -#define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018) -#define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C) - -#define S3C2416_PRIORITY_MODE1 S3C2410_IRQREG(0x030) -#define S3C2416_PRIORITY_UPDATE1 S3C2410_IRQREG(0x034) -#define S3C2416_SRCPND2 S3C2410_IRQREG(0x040) -#define S3C2416_INTMOD2 S3C2410_IRQREG(0x044) -#define S3C2416_INTMSK2 S3C2410_IRQREG(0x048) -#define S3C2416_INTPND2 S3C2410_IRQREG(0x050) -#define S3C2416_INTOFFSET2 S3C2410_IRQREG(0x054) -#define S3C2416_PRIORITY_MODE2 S3C2410_IRQREG(0x070) -#define S3C2416_PRIORITY_UPDATE2 S3C2410_IRQREG(0x074) - -/* mask: 0=enable, 1=disable - * 1 bit EINT, 4=EINT4, 23=EINT23 - * EINT0,1,2,3 are not handled here. -*/ - -#define S3C2410_EINTMASK S3C2410_EINTREG(0x0A4) -#define S3C2410_EINTPEND S3C2410_EINTREG(0X0A8) -#define S3C2412_EINTMASK S3C2410_EINTREG(0x0B4) -#define S3C2412_EINTPEND S3C2410_EINTREG(0X0B8) - -#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x0A4) -#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X0A8) - -#endif /* ___ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-lcd.h b/arch/arm/mach-s3c2410/include/mach/regs-lcd.h deleted file mode 100644 index ee8f040aff5f..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-lcd.h +++ /dev/null @@ -1,162 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-lcd.h - * - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - - -#ifndef ___ASM_ARCH_REGS_LCD_H -#define ___ASM_ARCH_REGS_LCD_H - -#define S3C2410_LCDREG(x) (x) - -/* LCD control registers */ -#define S3C2410_LCDCON1 S3C2410_LCDREG(0x00) -#define S3C2410_LCDCON2 S3C2410_LCDREG(0x04) -#define S3C2410_LCDCON3 S3C2410_LCDREG(0x08) -#define S3C2410_LCDCON4 S3C2410_LCDREG(0x0C) -#define S3C2410_LCDCON5 S3C2410_LCDREG(0x10) - -#define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8) -#define S3C2410_LCDCON1_MMODE (1<<7) -#define S3C2410_LCDCON1_DSCAN4 (0<<5) -#define S3C2410_LCDCON1_STN4 (1<<5) -#define S3C2410_LCDCON1_STN8 (2<<5) -#define S3C2410_LCDCON1_TFT (3<<5) - -#define S3C2410_LCDCON1_STN1BPP (0<<1) -#define S3C2410_LCDCON1_STN2GREY (1<<1) -#define S3C2410_LCDCON1_STN4GREY (2<<1) -#define S3C2410_LCDCON1_STN8BPP (3<<1) -#define S3C2410_LCDCON1_STN12BPP (4<<1) - -#define S3C2410_LCDCON1_TFT1BPP (8<<1) -#define S3C2410_LCDCON1_TFT2BPP (9<<1) -#define S3C2410_LCDCON1_TFT4BPP (10<<1) -#define S3C2410_LCDCON1_TFT8BPP (11<<1) -#define S3C2410_LCDCON1_TFT16BPP (12<<1) -#define S3C2410_LCDCON1_TFT24BPP (13<<1) - -#define S3C2410_LCDCON1_ENVID (1) - -#define S3C2410_LCDCON1_MODEMASK 0x1E - -#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) -#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14) -#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) -#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) - -#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF) -#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF) -#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F) - -#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) -#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) -#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8) -#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) -#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0) - -#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) -#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) - -/* LDCCON4 changes for STN mode on the S3C2412 */ - -#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) -#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) -#define S3C2410_LCDCON4_WLH(x) ((x) << 0) - -#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF) - -#define S3C2410_LCDCON5_BPP24BL (1<<12) -#define S3C2410_LCDCON5_FRM565 (1<<11) -#define S3C2410_LCDCON5_INVVCLK (1<<10) -#define S3C2410_LCDCON5_INVVLINE (1<<9) -#define S3C2410_LCDCON5_INVVFRAME (1<<8) -#define S3C2410_LCDCON5_INVVD (1<<7) -#define S3C2410_LCDCON5_INVVDEN (1<<6) -#define S3C2410_LCDCON5_INVPWREN (1<<5) -#define S3C2410_LCDCON5_INVLEND (1<<4) -#define S3C2410_LCDCON5_PWREN (1<<3) -#define S3C2410_LCDCON5_ENLEND (1<<2) -#define S3C2410_LCDCON5_BSWP (1<<1) -#define S3C2410_LCDCON5_HWSWP (1<<0) - -/* framebuffer start addressed */ -#define S3C2410_LCDSADDR1 S3C2410_LCDREG(0x14) -#define S3C2410_LCDSADDR2 S3C2410_LCDREG(0x18) -#define S3C2410_LCDSADDR3 S3C2410_LCDREG(0x1C) - -#define S3C2410_LCDBANK(x) ((x) << 21) -#define S3C2410_LCDBASEU(x) (x) - -#define S3C2410_OFFSIZE(x) ((x) << 11) -#define S3C2410_PAGEWIDTH(x) (x) - -/* colour lookup and miscellaneous controls */ - -#define S3C2410_REDLUT S3C2410_LCDREG(0x20) -#define S3C2410_GREENLUT S3C2410_LCDREG(0x24) -#define S3C2410_BLUELUT S3C2410_LCDREG(0x28) - -#define S3C2410_DITHMODE S3C2410_LCDREG(0x4C) -#define S3C2410_TPAL S3C2410_LCDREG(0x50) - -#define S3C2410_TPAL_EN (1<<24) - -/* interrupt info */ -#define S3C2410_LCDINTPND S3C2410_LCDREG(0x54) -#define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58) -#define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C) -#define S3C2410_LCDINT_FIWSEL (1<<2) -#define S3C2410_LCDINT_FRSYNC (1<<1) -#define S3C2410_LCDINT_FICNT (1<<0) - -/* s3c2442 extra stn registers */ - -#define S3C2442_REDLUT S3C2410_LCDREG(0x20) -#define S3C2442_GREENLUT S3C2410_LCDREG(0x24) -#define S3C2442_BLUELUT S3C2410_LCDREG(0x28) -#define S3C2442_DITHMODE S3C2410_LCDREG(0x20) - -#define S3C2410_LPCSEL S3C2410_LCDREG(0x60) - -#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4)) - -/* S3C2412 registers */ - -#define S3C2412_TPAL S3C2410_LCDREG(0x20) - -#define S3C2412_LCDINTPND S3C2410_LCDREG(0x24) -#define S3C2412_LCDSRCPND S3C2410_LCDREG(0x28) -#define S3C2412_LCDINTMSK S3C2410_LCDREG(0x2C) - -#define S3C2412_TCONSEL S3C2410_LCDREG(0x30) - -#define S3C2412_LCDCON6 S3C2410_LCDREG(0x34) -#define S3C2412_LCDCON7 S3C2410_LCDREG(0x38) -#define S3C2412_LCDCON8 S3C2410_LCDREG(0x3C) -#define S3C2412_LCDCON9 S3C2410_LCDREG(0x40) - -#define S3C2412_REDLUT(x) S3C2410_LCDREG(0x44 + ((x)*4)) -#define S3C2412_GREENLUT(x) S3C2410_LCDREG(0x60 + ((x)*4)) -#define S3C2412_BLUELUT(x) S3C2410_LCDREG(0x98 + ((x)*4)) - -#define S3C2412_FRCPAT(x) S3C2410_LCDREG(0xB4 + ((x)*4)) - -/* general registers */ - -/* base of the LCD registers, where INTPND, INTSRC and then INTMSK - * are available. */ - -#define S3C2410_LCDINTBASE S3C2410_LCDREG(0x54) -#define S3C2412_LCDINTBASE S3C2410_LCDREG(0x24) - -#define S3C24XX_LCDINTPND (0x00) -#define S3C24XX_LCDSRCPND (0x04) -#define S3C24XX_LCDINTMSK (0x08) - -#endif /* ___ASM_ARCH_REGS_LCD_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-mem.h deleted file mode 100644 index e0c67b0163d8..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-mem.h +++ /dev/null @@ -1,202 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-mem.h - * - * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 Memory Control register definitions -*/ - -#ifndef __ASM_ARM_MEMREGS_H -#define __ASM_ARM_MEMREGS_H - -#ifndef S3C2410_MEMREG -#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) -#endif - -/* bus width, and wait state control */ -#define S3C2410_BWSCON S3C2410_MEMREG(0x0000) - -/* bank zero config - note, pinstrapped from OM pins! */ -#define S3C2410_BWSCON_DW0_16 (1<<1) -#define S3C2410_BWSCON_DW0_32 (2<<1) - -/* bank one configs */ -#define S3C2410_BWSCON_DW1_8 (0<<4) -#define S3C2410_BWSCON_DW1_16 (1<<4) -#define S3C2410_BWSCON_DW1_32 (2<<4) -#define S3C2410_BWSCON_WS1 (1<<6) -#define S3C2410_BWSCON_ST1 (1<<7) - -/* bank 2 configurations */ -#define S3C2410_BWSCON_DW2_8 (0<<8) -#define S3C2410_BWSCON_DW2_16 (1<<8) -#define S3C2410_BWSCON_DW2_32 (2<<8) -#define S3C2410_BWSCON_WS2 (1<<10) -#define S3C2410_BWSCON_ST2 (1<<11) - -/* bank 3 configurations */ -#define S3C2410_BWSCON_DW3_8 (0<<12) -#define S3C2410_BWSCON_DW3_16 (1<<12) -#define S3C2410_BWSCON_DW3_32 (2<<12) -#define S3C2410_BWSCON_WS3 (1<<14) -#define S3C2410_BWSCON_ST3 (1<<15) - -/* bank 4 configurations */ -#define S3C2410_BWSCON_DW4_8 (0<<16) -#define S3C2410_BWSCON_DW4_16 (1<<16) -#define S3C2410_BWSCON_DW4_32 (2<<16) -#define S3C2410_BWSCON_WS4 (1<<18) -#define S3C2410_BWSCON_ST4 (1<<19) - -/* bank 5 configurations */ -#define S3C2410_BWSCON_DW5_8 (0<<20) -#define S3C2410_BWSCON_DW5_16 (1<<20) -#define S3C2410_BWSCON_DW5_32 (2<<20) -#define S3C2410_BWSCON_WS5 (1<<22) -#define S3C2410_BWSCON_ST5 (1<<23) - -/* bank 6 configurations */ -#define S3C2410_BWSCON_DW6_8 (0<<24) -#define S3C2410_BWSCON_DW6_16 (1<<24) -#define S3C2410_BWSCON_DW6_32 (2<<24) -#define S3C2410_BWSCON_WS6 (1<<26) -#define S3C2410_BWSCON_ST6 (1<<27) - -/* bank 7 configurations */ -#define S3C2410_BWSCON_DW7_8 (0<<28) -#define S3C2410_BWSCON_DW7_16 (1<<28) -#define S3C2410_BWSCON_DW7_32 (2<<28) -#define S3C2410_BWSCON_WS7 (1<<30) -#define S3C2410_BWSCON_ST7 (1<<31) - -/* accesor functions for getting BANK(n) configuration. (n != 0) */ - -#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf) - -#define S3C2410_BWSCON_DW8 (0) -#define S3C2410_BWSCON_DW16 (1) -#define S3C2410_BWSCON_DW32 (2) -#define S3C2410_BWSCON_WS (1 << 2) -#define S3C2410_BWSCON_ST (1 << 3) - -/* memory set (rom, ram) */ -#define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004) -#define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008) -#define S3C2410_BANKCON2 S3C2410_MEMREG(0x000C) -#define S3C2410_BANKCON3 S3C2410_MEMREG(0x0010) -#define S3C2410_BANKCON4 S3C2410_MEMREG(0x0014) -#define S3C2410_BANKCON5 S3C2410_MEMREG(0x0018) -#define S3C2410_BANKCON6 S3C2410_MEMREG(0x001C) -#define S3C2410_BANKCON7 S3C2410_MEMREG(0x0020) - -/* bank configuration registers */ - -#define S3C2410_BANKCON_PMCnorm (0x00) -#define S3C2410_BANKCON_PMC4 (0x01) -#define S3C2410_BANKCON_PMC8 (0x02) -#define S3C2410_BANKCON_PMC16 (0x03) - -/* bank configurations for banks 0..7, note banks - * 6 and 7 have different configurations depending on - * the memory type bits */ - -#define S3C2410_BANKCON_Tacp2 (0x0 << 2) -#define S3C2410_BANKCON_Tacp3 (0x1 << 2) -#define S3C2410_BANKCON_Tacp4 (0x2 << 2) -#define S3C2410_BANKCON_Tacp6 (0x3 << 2) -#define S3C2410_BANKCON_Tacp_SHIFT (2) - -#define S3C2410_BANKCON_Tcah0 (0x0 << 4) -#define S3C2410_BANKCON_Tcah1 (0x1 << 4) -#define S3C2410_BANKCON_Tcah2 (0x2 << 4) -#define S3C2410_BANKCON_Tcah4 (0x3 << 4) -#define S3C2410_BANKCON_Tcah_SHIFT (4) - -#define S3C2410_BANKCON_Tcoh0 (0x0 << 6) -#define S3C2410_BANKCON_Tcoh1 (0x1 << 6) -#define S3C2410_BANKCON_Tcoh2 (0x2 << 6) -#define S3C2410_BANKCON_Tcoh4 (0x3 << 6) -#define S3C2410_BANKCON_Tcoh_SHIFT (6) - -#define S3C2410_BANKCON_Tacc1 (0x0 << 8) -#define S3C2410_BANKCON_Tacc2 (0x1 << 8) -#define S3C2410_BANKCON_Tacc3 (0x2 << 8) -#define S3C2410_BANKCON_Tacc4 (0x3 << 8) -#define S3C2410_BANKCON_Tacc6 (0x4 << 8) -#define S3C2410_BANKCON_Tacc8 (0x5 << 8) -#define S3C2410_BANKCON_Tacc10 (0x6 << 8) -#define S3C2410_BANKCON_Tacc14 (0x7 << 8) -#define S3C2410_BANKCON_Tacc_SHIFT (8) - -#define S3C2410_BANKCON_Tcos0 (0x0 << 11) -#define S3C2410_BANKCON_Tcos1 (0x1 << 11) -#define S3C2410_BANKCON_Tcos2 (0x2 << 11) -#define S3C2410_BANKCON_Tcos4 (0x3 << 11) -#define S3C2410_BANKCON_Tcos_SHIFT (11) - -#define S3C2410_BANKCON_Tacs0 (0x0 << 13) -#define S3C2410_BANKCON_Tacs1 (0x1 << 13) -#define S3C2410_BANKCON_Tacs2 (0x2 << 13) -#define S3C2410_BANKCON_Tacs4 (0x3 << 13) -#define S3C2410_BANKCON_Tacs_SHIFT (13) - -#define S3C2410_BANKCON_SRAM (0x0 << 15) -#define S3C2410_BANKCON_SDRAM (0x3 << 15) - -/* next bits only for SDRAM in 6,7 */ -#define S3C2410_BANKCON_Trcd2 (0x00 << 2) -#define S3C2410_BANKCON_Trcd3 (0x01 << 2) -#define S3C2410_BANKCON_Trcd4 (0x02 << 2) - -/* control column address select */ -#define S3C2410_BANKCON_SCANb8 (0x00 << 0) -#define S3C2410_BANKCON_SCANb9 (0x01 << 0) -#define S3C2410_BANKCON_SCANb10 (0x02 << 0) - -#define S3C2410_REFRESH S3C2410_MEMREG(0x0024) -#define S3C2410_BANKSIZE S3C2410_MEMREG(0x0028) -#define S3C2410_MRSRB6 S3C2410_MEMREG(0x002C) -#define S3C2410_MRSRB7 S3C2410_MEMREG(0x0030) - -/* refresh control */ - -#define S3C2410_REFRESH_REFEN (1<<23) -#define S3C2410_REFRESH_SELF (1<<22) -#define S3C2410_REFRESH_REFCOUNTER ((1<<11)-1) - -#define S3C2410_REFRESH_TRP_MASK (3<<20) -#define S3C2410_REFRESH_TRP_2clk (0<<20) -#define S3C2410_REFRESH_TRP_3clk (1<<20) -#define S3C2410_REFRESH_TRP_4clk (2<<20) - -#define S3C2410_REFRESH_TSRC_MASK (3<<18) -#define S3C2410_REFRESH_TSRC_4clk (0<<18) -#define S3C2410_REFRESH_TSRC_5clk (1<<18) -#define S3C2410_REFRESH_TSRC_6clk (2<<18) -#define S3C2410_REFRESH_TSRC_7clk (3<<18) - - -/* mode select register(s) */ - -#define S3C2410_MRSRB_CL1 (0x00 << 4) -#define S3C2410_MRSRB_CL2 (0x02 << 4) -#define S3C2410_MRSRB_CL3 (0x03 << 4) - -/* bank size register */ -#define S3C2410_BANKSIZE_128M (0x2 << 0) -#define S3C2410_BANKSIZE_64M (0x1 << 0) -#define S3C2410_BANKSIZE_32M (0x0 << 0) -#define S3C2410_BANKSIZE_16M (0x7 << 0) -#define S3C2410_BANKSIZE_8M (0x6 << 0) -#define S3C2410_BANKSIZE_4M (0x5 << 0) -#define S3C2410_BANKSIZE_2M (0x4 << 0) -#define S3C2410_BANKSIZE_MASK (0x7 << 0) -#define S3C2410_BANKSIZE_SCLK_EN (1<<4) -#define S3C2410_BANKSIZE_SCKE_EN (1<<5) -#define S3C2410_BANKSIZE_BURST (1<<7) - -#endif /* __ASM_ARM_MEMREGS_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-power.h b/arch/arm/mach-s3c2410/include/mach/regs-power.h deleted file mode 100644 index 4932b87bdf3d..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-power.h +++ /dev/null @@ -1,40 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-power.h - * - * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C24XX power control register definitions -*/ - -#ifndef __ASM_ARM_REGS_PWR -#define __ASM_ARM_REGS_PWR __FILE__ - -#define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR) - -#define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20) -#define S3C2412_PWRCFG S3C24XX_PWRREG(0x24) - -#define S3C2412_INFORM0 S3C24XX_PWRREG(0x70) -#define S3C2412_INFORM1 S3C24XX_PWRREG(0x74) -#define S3C2412_INFORM2 S3C24XX_PWRREG(0x78) -#define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C) - -#define S3C2412_PWRCFG_BATF_IRQ (1<<0) -#define S3C2412_PWRCFG_BATF_IGNORE (2<<0) -#define S3C2412_PWRCFG_BATF_SLEEP (3<<0) -#define S3C2412_PWRCFG_BATF_MASK (3<<0) - -#define S3C2412_PWRCFG_STANDBYWFI_IGNORE (0<<6) -#define S3C2412_PWRCFG_STANDBYWFI_IDLE (1<<6) -#define S3C2412_PWRCFG_STANDBYWFI_STOP (2<<6) -#define S3C2412_PWRCFG_STANDBYWFI_SLEEP (3<<6) -#define S3C2412_PWRCFG_STANDBYWFI_MASK (3<<6) - -#define S3C2412_PWRCFG_RTC_MASKIRQ (1<<8) -#define S3C2412_PWRCFG_NAND_NORST (1<<9) - -#endif /* __ASM_ARM_REGS_PWR */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h deleted file mode 100644 index fb6352515090..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h +++ /dev/null @@ -1,48 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h - * - * Copyright (c) 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2412 memory register definitions -*/ - -#ifndef __ASM_ARM_REGS_S3C2412_MEM -#define __ASM_ARM_REGS_S3C2412_MEM - -#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) -#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x)) - -#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x)) -#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o))) - -#define S3C2412_BANKCFG S3C2412_MEMREG(0x00) -#define S3C2412_BANKCON1 S3C2412_MEMREG(0x04) -#define S3C2412_BANKCON2 S3C2412_MEMREG(0x08) -#define S3C2412_BANKCON3 S3C2412_MEMREG(0x0C) - -#define S3C2412_REFRESH S3C2412_MEMREG(0x10) -#define S3C2412_TIMEOUT S3C2412_MEMREG(0x14) - -/* EBI control registers */ - -#define S3C2412_EBI_PR S3C2412_EBIREG(0x00) -#define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x04) - -/* SSMC control registers */ - -#define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x00) -#define S3C2412_SMIDCYR(x) S3C2412_SSMC(x, 0x00) -#define S3C2412_SMBWSTRD(x) S3C2412_SSMC(x, 0x04) -#define S3C2412_SMBWSTWRR(x) S3C2412_SSMC(x, 0x08) -#define S3C2412_SMBWSTOENR(x) S3C2412_SSMC(x, 0x0C) -#define S3C2412_SMBWSTWENR(x) S3C2412_SSMC(x, 0x10) -#define S3C2412_SMBCR(x) S3C2412_SSMC(x, 0x14) -#define S3C2412_SMBSR(x) S3C2412_SSMC(x, 0x18) -#define S3C2412_SMBWSTBRDR(x) S3C2412_SSMC(x, 0x1C) - -#endif /* __ASM_ARM_REGS_S3C2412_MEM */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h deleted file mode 100644 index aa69dc79bc38..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h +++ /dev/null @@ -1,23 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h - * - * Copyright 2007 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2412 specific register definitions -*/ - -#ifndef __ASM_ARCH_REGS_S3C2412_H -#define __ASM_ARCH_REGS_S3C2412_H "s3c2412" - -#define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30) -#define S3C2412_SWRST_RESET (0x533C2412) - -/* see regs-power.h for the other registers in the power block. */ - -#endif /* __ASM_ARCH_REGS_S3C2412_H */ - diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h deleted file mode 100644 index 2f31b74974af..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h +++ /dev/null @@ -1,30 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h - * - * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>, - * as part of OpenInkpot project - * Copyright (c) 2009 Promwad Innovation Company - * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2416 memory register definitions -*/ - -#ifndef __ASM_ARM_REGS_S3C2416_MEM -#define __ASM_ARM_REGS_S3C2416_MEM - -#ifndef S3C2416_MEMREG -#define S3C2416_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) -#endif - -#define S3C2416_BANKCFG S3C2416_MEMREG(0x00) -#define S3C2416_BANKCON1 S3C2416_MEMREG(0x04) -#define S3C2416_BANKCON2 S3C2416_MEMREG(0x08) -#define S3C2416_BANKCON3 S3C2416_MEMREG(0x0C) - -#define S3C2416_REFRESH S3C2416_MEMREG(0x10) -#define S3C2416_TIMEOUT S3C2416_MEMREG(0x14) - -#endif /* __ASM_ARM_REGS_S3C2416_MEM */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h deleted file mode 100644 index e443167efb87..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h +++ /dev/null @@ -1,24 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h - * - * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>, - * as part of OpenInkpot project - * Copyright (c) 2009 Promwad Innovation Company - * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2416 specific register definitions -*/ - -#ifndef __ASM_ARCH_REGS_S3C2416_H -#define __ASM_ARCH_REGS_S3C2416_H "s3c2416" - -#define S3C2416_SWRST (S3C24XX_VA_CLKPWR + 0x44) -#define S3C2416_SWRST_RESET (0x533C2416) - -/* see regs-power.h for the other registers in the power block. */ - -#endif /* __ASM_ARCH_REGS_S3C2416_H */ - diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h deleted file mode 100644 index c3feff3c0488..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h +++ /dev/null @@ -1,194 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h - * - * Copyright (c) 2007 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2443 clock register definitions -*/ - -#ifndef __ASM_ARM_REGS_S3C2443_CLOCK -#define __ASM_ARM_REGS_S3C2443_CLOCK - -#define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR) - -#define S3C2443_PLLCON_MDIVSHIFT 16 -#define S3C2443_PLLCON_PDIVSHIFT 8 -#define S3C2443_PLLCON_SDIVSHIFT 0 -#define S3C2443_PLLCON_MDIVMASK ((1<<(1+(23-16)))-1) -#define S3C2443_PLLCON_PDIVMASK ((1<<(1+(9-8)))-1) -#define S3C2443_PLLCON_SDIVMASK (3) - -#define S3C2443_MPLLCON S3C2443_CLKREG(0x10) -#define S3C2443_EPLLCON S3C2443_CLKREG(0x18) -#define S3C2443_CLKSRC S3C2443_CLKREG(0x20) -#define S3C2443_CLKDIV0 S3C2443_CLKREG(0x24) -#define S3C2443_CLKDIV1 S3C2443_CLKREG(0x28) -#define S3C2443_HCLKCON S3C2443_CLKREG(0x30) -#define S3C2443_PCLKCON S3C2443_CLKREG(0x34) -#define S3C2443_SCLKCON S3C2443_CLKREG(0x38) -#define S3C2443_PWRMODE S3C2443_CLKREG(0x40) -#define S3C2443_SWRST S3C2443_CLKREG(0x44) -#define S3C2443_BUSPRI0 S3C2443_CLKREG(0x50) -#define S3C2443_SYSID S3C2443_CLKREG(0x5C) -#define S3C2443_PWRCFG S3C2443_CLKREG(0x60) -#define S3C2443_RSTCON S3C2443_CLKREG(0x64) -#define S3C2443_PHYCTRL S3C2443_CLKREG(0x80) -#define S3C2443_PHYPWR S3C2443_CLKREG(0x84) -#define S3C2443_URSTCON S3C2443_CLKREG(0x88) -#define S3C2443_UCLKCON S3C2443_CLKREG(0x8C) - -#define S3C2443_SWRST_RESET (0x533c2443) - -#define S3C2443_PLLCON_OFF (1<<24) - -#define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7) -#define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<7) -#define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<7) -#define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<7) -#define S3C2443_CLKSRC_EPLLREF_MASK (3<<7) - -#define S3C2443_CLKSRC_EXTCLK_DIV (1<<3) - -#define S3C2443_CLKDIV0_HALF_HCLK (1<<3) -#define S3C2443_CLKDIV0_HALF_PCLK (1<<2) - -#define S3C2443_CLKDIV0_HCLKDIV_MASK (3<<0) - -#define S3C2443_CLKDIV0_EXTDIV_MASK (3<<6) -#define S3C2443_CLKDIV0_EXTDIV_SHIFT (6) - -#define S3C2443_CLKDIV0_PREDIV_MASK (3<<4) -#define S3C2443_CLKDIV0_PREDIV_SHIFT (4) - -#define S3C2416_CLKDIV0_ARMDIV_MASK (7 << 9) -#define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9) -#define S3C2443_CLKDIV0_ARMDIV_SHIFT (9) -#define S3C2443_CLKDIV0_ARMDIV_1 (0<<9) -#define S3C2443_CLKDIV0_ARMDIV_2 (8<<9) -#define S3C2443_CLKDIV0_ARMDIV_3 (2<<9) -#define S3C2443_CLKDIV0_ARMDIV_4 (9<<9) -#define S3C2443_CLKDIV0_ARMDIV_6 (10<<9) -#define S3C2443_CLKDIV0_ARMDIV_8 (11<<9) -#define S3C2443_CLKDIV0_ARMDIV_12 (13<<9) -#define S3C2443_CLKDIV0_ARMDIV_16 (15<<9) - -/* S3C2443_CLKDIV1 removed, only used in clock.c code */ - -#define S3C2443_CLKCON_NAND - -#define S3C2443_HCLKCON_DMA0 (1<<0) -#define S3C2443_HCLKCON_DMA1 (1<<1) -#define S3C2443_HCLKCON_DMA2 (1<<2) -#define S3C2443_HCLKCON_DMA3 (1<<3) -#define S3C2443_HCLKCON_DMA4 (1<<4) -#define S3C2443_HCLKCON_DMA5 (1<<5) -#define S3C2443_HCLKCON_CAMIF (1<<8) -#define S3C2443_HCLKCON_LCDC (1<<9) -#define S3C2443_HCLKCON_USBH (1<<11) -#define S3C2443_HCLKCON_USBD (1<<12) -#define S3C2416_HCLKCON_HSMMC0 (1<<15) -#define S3C2443_HCLKCON_HSMMC (1<<16) -#define S3C2443_HCLKCON_CFC (1<<17) -#define S3C2443_HCLKCON_SSMC (1<<18) -#define S3C2443_HCLKCON_DRAMC (1<<19) - -#define S3C2443_PCLKCON_UART0 (1<<0) -#define S3C2443_PCLKCON_UART1 (1<<1) -#define S3C2443_PCLKCON_UART2 (1<<2) -#define S3C2443_PCLKCON_UART3 (1<<3) -#define S3C2443_PCLKCON_IIC (1<<4) -#define S3C2443_PCLKCON_SDI (1<<5) -#define S3C2443_PCLKCON_HSSPI (1<<6) -#define S3C2443_PCLKCON_ADC (1<<7) -#define S3C2443_PCLKCON_AC97 (1<<8) -#define S3C2443_PCLKCON_IIS (1<<9) -#define S3C2443_PCLKCON_PWMT (1<<10) -#define S3C2443_PCLKCON_WDT (1<<11) -#define S3C2443_PCLKCON_RTC (1<<12) -#define S3C2443_PCLKCON_GPIO (1<<13) -#define S3C2443_PCLKCON_SPI0 (1<<14) -#define S3C2443_PCLKCON_SPI1 (1<<15) - -#define S3C2443_SCLKCON_DDRCLK (1<<16) -#define S3C2443_SCLKCON_SSMCCLK (1<<15) -#define S3C2443_SCLKCON_HSSPICLK (1<<14) -#define S3C2443_SCLKCON_HSMMCCLK_EXT (1<<13) -#define S3C2443_SCLKCON_HSMMCCLK_EPLL (1<<12) -#define S3C2443_SCLKCON_CAMCLK (1<<11) -#define S3C2443_SCLKCON_DISPCLK (1<<10) -#define S3C2443_SCLKCON_I2SCLK (1<<9) -#define S3C2443_SCLKCON_UARTCLK (1<<8) -#define S3C2443_SCLKCON_USBHOST (1<<1) - -#define S3C2443_PWRCFG_SLEEP (1<<15) - -#define S3C2443_PWRCFG_USBPHY (1 << 4) - -#define S3C2443_URSTCON_FUNCRST (1 << 2) -#define S3C2443_URSTCON_PHYRST (1 << 0) - -#define S3C2443_PHYCTRL_CLKSEL (1 << 3) -#define S3C2443_PHYCTRL_EXTCLK (1 << 2) -#define S3C2443_PHYCTRL_PLLSEL (1 << 1) -#define S3C2443_PHYCTRL_DSPORT (1 << 0) - -#define S3C2443_PHYPWR_COMMON_ON (1 << 31) -#define S3C2443_PHYPWR_ANALOG_PD (1 << 4) -#define S3C2443_PHYPWR_PLL_REFCLK (1 << 3) -#define S3C2443_PHYPWR_XO_ON (1 << 2) -#define S3C2443_PHYPWR_PLL_PWRDN (1 << 1) -#define S3C2443_PHYPWR_FSUSPEND (1 << 0) - -#define S3C2443_UCLKCON_DETECT_VBUS (1 << 31) -#define S3C2443_UCLKCON_FUNC_CLKEN (1 << 2) -#define S3C2443_UCLKCON_TCLKEN (1 << 0) - -#include <asm/div64.h> - -static inline unsigned int -s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk) -{ - unsigned int mdiv, pdiv, sdiv; - uint64_t fvco; - - mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; - pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT; - sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT; - - mdiv &= S3C2443_PLLCON_MDIVMASK; - pdiv &= S3C2443_PLLCON_PDIVMASK; - sdiv &= S3C2443_PLLCON_SDIVMASK; - - fvco = (uint64_t)baseclk * (2 * (mdiv + 8)); - do_div(fvco, pdiv << sdiv); - - return (unsigned int)fvco; -} - -static inline unsigned int -s3c2443_get_epll(unsigned int pllval, unsigned int baseclk) -{ - unsigned int mdiv, pdiv, sdiv; - uint64_t fvco; - - mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; - pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT; - sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT; - - mdiv &= S3C2443_PLLCON_MDIVMASK; - pdiv &= S3C2443_PLLCON_PDIVMASK; - sdiv &= S3C2443_PLLCON_SDIVMASK; - - fvco = (uint64_t)baseclk * (mdiv + 8); - do_div(fvco, (pdiv + 2) << sdiv); - - return (unsigned int)fvco; -} - -#endif /* __ASM_ARM_REGS_S3C2443_CLOCK */ - diff --git a/arch/arm/mach-s3c2410/include/mach/regs-sdi.h b/arch/arm/mach-s3c2410/include/mach/regs-sdi.h deleted file mode 100644 index cbf2d8884e30..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-sdi.h +++ /dev/null @@ -1,127 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-sdi.h - * - * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 MMC/SDIO register definitions -*/ - -#ifndef __ASM_ARM_REGS_SDI -#define __ASM_ARM_REGS_SDI "regs-sdi.h" - -#define S3C2410_SDICON (0x00) -#define S3C2410_SDIPRE (0x04) -#define S3C2410_SDICMDARG (0x08) -#define S3C2410_SDICMDCON (0x0C) -#define S3C2410_SDICMDSTAT (0x10) -#define S3C2410_SDIRSP0 (0x14) -#define S3C2410_SDIRSP1 (0x18) -#define S3C2410_SDIRSP2 (0x1C) -#define S3C2410_SDIRSP3 (0x20) -#define S3C2410_SDITIMER (0x24) -#define S3C2410_SDIBSIZE (0x28) -#define S3C2410_SDIDCON (0x2C) -#define S3C2410_SDIDCNT (0x30) -#define S3C2410_SDIDSTA (0x34) -#define S3C2410_SDIFSTA (0x38) - -#define S3C2410_SDIDATA (0x3C) -#define S3C2410_SDIIMSK (0x40) - -#define S3C2440_SDIDATA (0x40) -#define S3C2440_SDIIMSK (0x3C) - -#define S3C2440_SDICON_SDRESET (1<<8) -#define S3C2440_SDICON_MMCCLOCK (1<<5) -#define S3C2410_SDICON_BYTEORDER (1<<4) -#define S3C2410_SDICON_SDIOIRQ (1<<3) -#define S3C2410_SDICON_RWAITEN (1<<2) -#define S3C2410_SDICON_FIFORESET (1<<1) -#define S3C2410_SDICON_CLOCKTYPE (1<<0) - -#define S3C2410_SDICMDCON_ABORT (1<<12) -#define S3C2410_SDICMDCON_WITHDATA (1<<11) -#define S3C2410_SDICMDCON_LONGRSP (1<<10) -#define S3C2410_SDICMDCON_WAITRSP (1<<9) -#define S3C2410_SDICMDCON_CMDSTART (1<<8) -#define S3C2410_SDICMDCON_SENDERHOST (1<<6) -#define S3C2410_SDICMDCON_INDEX (0x3f) - -#define S3C2410_SDICMDSTAT_CRCFAIL (1<<12) -#define S3C2410_SDICMDSTAT_CMDSENT (1<<11) -#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10) -#define S3C2410_SDICMDSTAT_RSPFIN (1<<9) -#define S3C2410_SDICMDSTAT_XFERING (1<<8) -#define S3C2410_SDICMDSTAT_INDEX (0xff) - -#define S3C2440_SDIDCON_DS_BYTE (0<<22) -#define S3C2440_SDIDCON_DS_HALFWORD (1<<22) -#define S3C2440_SDIDCON_DS_WORD (2<<22) -#define S3C2410_SDIDCON_IRQPERIOD (1<<21) -#define S3C2410_SDIDCON_TXAFTERRESP (1<<20) -#define S3C2410_SDIDCON_RXAFTERCMD (1<<19) -#define S3C2410_SDIDCON_BUSYAFTERCMD (1<<18) -#define S3C2410_SDIDCON_BLOCKMODE (1<<17) -#define S3C2410_SDIDCON_WIDEBUS (1<<16) -#define S3C2410_SDIDCON_DMAEN (1<<15) -#define S3C2410_SDIDCON_STOP (1<<14) -#define S3C2440_SDIDCON_DATSTART (1<<14) -#define S3C2410_SDIDCON_DATMODE (3<<12) -#define S3C2410_SDIDCON_BLKNUM (0x7ff) - -/* constants for S3C2410_SDIDCON_DATMODE */ -#define S3C2410_SDIDCON_XFER_READY (0<<12) -#define S3C2410_SDIDCON_XFER_CHKSTART (1<<12) -#define S3C2410_SDIDCON_XFER_RXSTART (2<<12) -#define S3C2410_SDIDCON_XFER_TXSTART (3<<12) - -#define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF) -#define S3C2410_SDIDCNT_BLKNUM_SHIFT (12) - -#define S3C2410_SDIDSTA_RDYWAITREQ (1<<10) -#define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9) -#define S3C2410_SDIDSTA_FIFOFAIL (1<<8) /* reserved on 2440 */ -#define S3C2410_SDIDSTA_CRCFAIL (1<<7) -#define S3C2410_SDIDSTA_RXCRCFAIL (1<<6) -#define S3C2410_SDIDSTA_DATATIMEOUT (1<<5) -#define S3C2410_SDIDSTA_XFERFINISH (1<<4) -#define S3C2410_SDIDSTA_BUSYFINISH (1<<3) -#define S3C2410_SDIDSTA_SBITERR (1<<2) /* reserved on 2410a/2440 */ -#define S3C2410_SDIDSTA_TXDATAON (1<<1) -#define S3C2410_SDIDSTA_RXDATAON (1<<0) - -#define S3C2440_SDIFSTA_FIFORESET (1<<16) -#define S3C2440_SDIFSTA_FIFOFAIL (3<<14) /* 3 is correct (2 bits) */ -#define S3C2410_SDIFSTA_TFDET (1<<13) -#define S3C2410_SDIFSTA_RFDET (1<<12) -#define S3C2410_SDIFSTA_TFHALF (1<<11) -#define S3C2410_SDIFSTA_TFEMPTY (1<<10) -#define S3C2410_SDIFSTA_RFLAST (1<<9) -#define S3C2410_SDIFSTA_RFFULL (1<<8) -#define S3C2410_SDIFSTA_RFHALF (1<<7) -#define S3C2410_SDIFSTA_COUNTMASK (0x7f) - -#define S3C2410_SDIIMSK_RESPONSECRC (1<<17) -#define S3C2410_SDIIMSK_CMDSENT (1<<16) -#define S3C2410_SDIIMSK_CMDTIMEOUT (1<<15) -#define S3C2410_SDIIMSK_RESPONSEND (1<<14) -#define S3C2410_SDIIMSK_READWAIT (1<<13) -#define S3C2410_SDIIMSK_SDIOIRQ (1<<12) -#define S3C2410_SDIIMSK_FIFOFAIL (1<<11) -#define S3C2410_SDIIMSK_CRCSTATUS (1<<10) -#define S3C2410_SDIIMSK_DATACRC (1<<9) -#define S3C2410_SDIIMSK_DATATIMEOUT (1<<8) -#define S3C2410_SDIIMSK_DATAFINISH (1<<7) -#define S3C2410_SDIIMSK_BUSYFINISH (1<<6) -#define S3C2410_SDIIMSK_SBITERR (1<<5) /* reserved 2440/2410a */ -#define S3C2410_SDIIMSK_TXFIFOHALF (1<<4) -#define S3C2410_SDIIMSK_TXFIFOEMPTY (1<<3) -#define S3C2410_SDIIMSK_RXFIFOLAST (1<<2) -#define S3C2410_SDIIMSK_RXFIFOFULL (1<<1) -#define S3C2410_SDIIMSK_RXFIFOHALF (1<<0) - -#endif /* __ASM_ARM_REGS_SDI */ diff --git a/arch/arm/mach-s3c2410/include/mach/spi.h b/arch/arm/mach-s3c2410/include/mach/spi.h deleted file mode 100644 index 4d9588373aa5..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/spi.h +++ /dev/null @@ -1,38 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/spi.h - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - SPI Controller platform_device info - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_SPI_H -#define __ASM_ARCH_SPI_H __FILE__ - -struct s3c2410_spi_info { - int pin_cs; /* simple gpio cs */ - unsigned int num_cs; /* total chipselects */ - int bus_num; /* bus number to use. */ - - unsigned int use_fiq:1; /* use fiq */ - - void (*gpio_setup)(struct s3c2410_spi_info *spi, int enable); - void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol); -}; - -/* Standard setup / suspend routines for SPI GPIO pins. */ - -extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi, - int enable); - -extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi, - int enable); - -extern void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi, - int enable); - -#endif /* __ASM_ARCH_SPI_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/tick.h b/arch/arm/mach-s3c2410/include/mach/tick.h deleted file mode 100644 index 544da41979db..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/tick.h +++ /dev/null @@ -1,15 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/include/mach/tick.h - * - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C2410 - timer tick support - */ - -#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0)) - -static inline int s3c24xx_ostimer_pending(void) -{ - return __raw_readl(S3C2410_SRCPND) & SRCPND_TIMER4; -} diff --git a/arch/arm/mach-s3c2410/include/mach/timex.h b/arch/arm/mach-s3c2410/include/mach/timex.h deleted file mode 100644 index fe9ca1ffd51b..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/timex.h +++ /dev/null @@ -1,24 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/timex.h - * - * Copyright (c) 2003-2005 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - time parameters - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it - * a variable is useless. It seems as long as we make our timers an - * exact multiple of HZ, any value that makes a 1->1 correspondence - * for the time conversion functions to/from jiffies is acceptable. -*/ - -#define CLOCK_TICK_RATE 12000000 - -#endif /* __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/uncompress.h b/arch/arm/mach-s3c2410/include/mach/uncompress.h deleted file mode 100644 index 8b283f847daa..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/uncompress.h +++ /dev/null @@ -1,54 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/uncompress.h - * - * Copyright (c) 2003-2007 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - uncompress code - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include <mach/regs-gpio.h> -#include <mach/map.h> - -/* working in physical space... */ -#undef S3C2410_GPIOREG -#define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x))) - -#include <plat/uncompress.h> - -static inline int is_arm926(void) -{ - unsigned int cpuid; - - asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (cpuid)); - - return ((cpuid & 0xff0) == 0x260); -} - -static void arch_detect_cpu(void) -{ - unsigned int cpuid; - - cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1); - cpuid &= S3C2410_GSTATUS1_IDMASK; - - if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 || - cpuid == S3C2410_GSTATUS1_2442 || - cpuid == S3C2410_GSTATUS1_2416 || - cpuid == S3C2410_GSTATUS1_2450) { - fifo_mask = S3C2440_UFSTAT_TXMASK; - fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; - } else { - fifo_mask = S3C2410_UFSTAT_TXMASK; - fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT; - } -} - -#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h b/arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h deleted file mode 100644 index e4119913d7c5..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h +++ /dev/null @@ -1,18 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h - * - * Copyright (c) 2003 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * VR1000 - CPLD control constants - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_VR1000CPLD_H -#define __ASM_ARCH_VR1000CPLD_H - -#define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */ - -#endif /* __ASM_ARCH_VR1000CPLD_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h b/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h deleted file mode 100644 index 47add133b8ee..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h +++ /dev/null @@ -1,26 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/vr1000-irq.h - * - * Copyright (c) 2003-2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Machine VR1000 - IRQ Number definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_VR1000IRQ_H -#define __ASM_ARCH_VR1000IRQ_H - -/* irq numbers to onboard peripherals */ - -#define IRQ_USBOC IRQ_EINT19 -#define IRQ_IDE0 IRQ_EINT16 -#define IRQ_IDE1 IRQ_EINT17 -#define IRQ_VR1000_SERIAL IRQ_EINT12 -#define IRQ_VR1000_DM9000A IRQ_EINT10 -#define IRQ_VR1000_DM9000N IRQ_EINT9 -#define IRQ_SMALERT IRQ_EINT8 - -#endif /* __ASM_ARCH_VR1000IRQ_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-map.h b/arch/arm/mach-s3c2410/include/mach/vr1000-map.h deleted file mode 100644 index 99612fcc4eb2..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/vr1000-map.h +++ /dev/null @@ -1,110 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/vr1000-map.h - * - * Copyright (c) 2003-2005 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Machine VR1000 - Memory map definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* needs arch/map.h including with this */ - -/* ok, we've used up to 0x13000000, now we need to find space for the - * peripherals that live in the nGCS[x] areas, which are quite numerous - * in their space. We also have the board's CPLD to find register space - * for. - */ - -#ifndef __ASM_ARCH_VR1000MAP_H -#define __ASM_ARCH_VR1000MAP_H - -#include <mach/bast-map.h> - -#define VR1000_IOADDR(x) BAST_IOADDR(x) - -/* we put the CPLD registers next, to get them out of the way */ - -#define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */ -#define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000) - -#define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */ -#define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000) - -#define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */ -#define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000) - -#define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */ -#define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000) - -/* next, we have the PC104 ISA interrupt registers */ - -#define VR1000_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */ -#define VR1000_VA_PC104_IRQREQ VR1000_IOADDR(0x00400000) - -#define VR1000_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */ -#define VR1000_VA_PC104_IRQRAW VR1000_IOADDR(0x00500000) - -#define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */ -#define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000) - -/* 0xE0000000 contains the IO space that is split by speed and - * wether the access is for 8 or 16bit IO... this ensures that - * the correct access is made - * - * 0x10000000 of space, partitioned as so: - * - * 0x00000000 to 0x04000000 8bit, slow - * 0x04000000 to 0x08000000 16bit, slow - * 0x08000000 to 0x0C000000 16bit, net - * 0x0C000000 to 0x10000000 16bit, fast - * - * each of these spaces has the following in: - * - * 0x02000000 to 0x02100000 1MB IDE primary channel - * 0x02100000 to 0x02200000 1MB IDE primary channel aux - * 0x02200000 to 0x02400000 1MB IDE secondary channel - * 0x02300000 to 0x02400000 1MB IDE secondary channel aux - * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controllers - * 0x02600000 to 0x02700000 1MB - * - * the phyiscal layout of the zones are: - * nGCS2 - 8bit, slow - * nGCS3 - 16bit, slow - * nGCS4 - 16bit, net - * nGCS5 - 16bit, fast - */ - -#define VR1000_VA_MULTISPACE (0xE0000000) - -#define VR1000_VA_ISAIO (VR1000_VA_MULTISPACE + 0x00000000) -#define VR1000_VA_ISAMEM (VR1000_VA_MULTISPACE + 0x01000000) -#define VR1000_VA_IDEPRI (VR1000_VA_MULTISPACE + 0x02000000) -#define VR1000_VA_IDEPRIAUX (VR1000_VA_MULTISPACE + 0x02100000) -#define VR1000_VA_IDESEC (VR1000_VA_MULTISPACE + 0x02200000) -#define VR1000_VA_IDESECAUX (VR1000_VA_MULTISPACE + 0x02300000) -#define VR1000_VA_ASIXNET (VR1000_VA_MULTISPACE + 0x02400000) -#define VR1000_VA_DM9000 (VR1000_VA_MULTISPACE + 0x02500000) -#define VR1000_VA_SUPERIO (VR1000_VA_MULTISPACE + 0x02600000) - -/* physical offset addresses for the peripherals */ - -#define VR1000_PA_IDEPRI (0x02000000) -#define VR1000_PA_IDEPRIAUX (0x02800000) -#define VR1000_PA_IDESEC (0x03000000) -#define VR1000_PA_IDESECAUX (0x03800000) -#define VR1000_PA_DM9000 (0x05000000) - -#define VR1000_PA_SERIAL (0x11800000) -#define VR1000_VA_SERIAL (VR1000_IOADDR(0x00700000)) - -/* VR1000 ram is in CS1, with A26..A24 = 2_101 */ -#define VR1000_PA_SRAM (S3C2410_CS1 | 0x05000000) - -/* some configurations for the peripherals */ - -#define VR1000_DM9000_CS VR1000_VAM_CS4 - -#endif /* __ASM_ARCH_VR1000MAP_H */ |
