diff options
Diffstat (limited to 'arch/arm/mach-iop33x')
21 files changed, 398 insertions, 7 deletions
diff --git a/arch/arm/mach-iop33x/include/mach/adma.h b/arch/arm/mach-iop33x/include/mach/adma.h new file mode 100644 index 000000000000..4b92f795f90e --- /dev/null +++ b/arch/arm/mach-iop33x/include/mach/adma.h @@ -0,0 +1,5 @@ +#ifndef IOP33X_ADMA_H +#define IOP33X_ADMA_H +#include <asm/hardware/iop3xx-adma.h> +#endif + diff --git a/arch/arm/mach-iop33x/include/mach/debug-macro.S b/arch/arm/mach-iop33x/include/mach/debug-macro.S new file mode 100644 index 000000000000..a60c9ef05cc3 --- /dev/null +++ b/arch/arm/mach-iop33x/include/mach/debug-macro.S @@ -0,0 +1,24 @@ +/* + * arch/arm/mach-iop33x/include/mach/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + .macro addruart, rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ mmu enabled? + moveq \rx, #0xff000000 @ physical + movne \rx, #0xfe000000 @ virtual + orr \rx, \rx, #0x00ff0000 + orr \rx, \rx, #0x0000f700 + .endm + +#define UART_SHIFT 2 +#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-iop33x/include/mach/dma.h b/arch/arm/mach-iop33x/include/mach/dma.h new file mode 100644 index 000000000000..d8b42232931d --- /dev/null +++ b/arch/arm/mach-iop33x/include/mach/dma.h @@ -0,0 +1,9 @@ +/* + * arch/arm/mach-iop33x/include/mach/dma.h + * + * Copyright (C) 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ diff --git a/arch/arm/mach-iop33x/include/mach/entry-macro.S b/arch/arm/mach-iop33x/include/mach/entry-macro.S new file mode 100644 index 000000000000..4e1f7282b354 --- /dev/null +++ b/arch/arm/mach-iop33x/include/mach/entry-macro.S @@ -0,0 +1,37 @@ +/* + * arch/arm/mach-iop33x/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for IOP33x-based platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include <mach/iop33x.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + mrc p15, 0, \tmp, c15, c1, 0 + orr \tmp, \tmp, #(1 << 6) + mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access + mrc p15, 0, \tmp, c15, c1, 0 + mov \tmp, \tmp + sub pc, pc, #4 @ cp_wait + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + mrc p6, 0, \irqstat, c14, c0, 0 @ Read IINTVEC + cmp \irqstat, #0 + mrceq p6, 0, \irqstat, c14, c0, 0 @ erratum 63 workaround + adds \irqnr, \irqstat, #1 + movne \irqnr, \irqstat, lsr #2 + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + mrc p15, 0, \tmp1, c15, c1, 0 + ands \tmp2, \tmp1, #(1 << 6) + bicne \tmp1, \tmp1, #(1 << 6) + mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access + .endm diff --git a/arch/arm/mach-iop33x/include/mach/gpio.h b/arch/arm/mach-iop33x/include/mach/gpio.h new file mode 100644 index 000000000000..ddd55bba9bb9 --- /dev/null +++ b/arch/arm/mach-iop33x/include/mach/gpio.h @@ -0,0 +1,6 @@ +#ifndef __ASM_ARCH_IOP33X_GPIO_H +#define __ASM_ARCH_IOP33X_GPIO_H + +#include <asm/hardware/iop3xx-gpio.h> + +#endif diff --git a/arch/arm/mach-iop33x/include/mach/hardware.h b/arch/arm/mach-iop33x/include/mach/hardware.h new file mode 100644 index 000000000000..8c10e430655e --- /dev/null +++ b/arch/arm/mach-iop33x/include/mach/hardware.h @@ -0,0 +1,46 @@ +/* + * arch/arm/mach-iop33x/include/mach/hardware.h + */ + +#ifndef __HARDWARE_H +#define __HARDWARE_H + +#include <asm/types.h> + +/* + * Note about PCI IO space mappings + * + * To make IO space accesses efficient, we store virtual addresses in + * the IO resources. + * + * The PCI IO space is located at virtual 0xfe000000 from physical + * 0x90000000. The PCI BARs must be programmed with physical addresses, + * but when we read them, we convert them to virtual addresses. See + * arch/arm/mach-iop3xx/iop3xx-pci.c + */ +#define pcibios_assign_all_busses() 1 +#define PCIBIOS_MIN_IO 0x00000000 +#define PCIBIOS_MIN_MEM 0x00000000 + +#ifndef __ASSEMBLY__ +void iop33x_init_irq(void); + +extern struct platform_device iop33x_uart0_device; +extern struct platform_device iop33x_uart1_device; +#endif + + +/* + * Generic chipset bits + * + */ +#include "iop33x.h" + +/* + * Board specific bits + */ +#include "iq80331.h" +#include "iq80332.h" + + +#endif diff --git a/arch/arm/mach-iop33x/include/mach/io.h b/arch/arm/mach-iop33x/include/mach/io.h new file mode 100644 index 000000000000..158874631217 --- /dev/null +++ b/arch/arm/mach-iop33x/include/mach/io.h @@ -0,0 +1,27 @@ +/* + * arch/arm/mach-iop33x/include/mach/io.h + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __IO_H +#define __IO_H + +#include <mach/hardware.h> + +extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, + unsigned int mtype); +extern void __iop3xx_iounmap(void __iomem *addr); + +#define IO_SPACE_LIMIT 0xffffffff +#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p)) +#define __mem_pci(a) (a) + +#define __arch_ioremap(a, s, f) __iop3xx_ioremap(a, s, f) +#define __arch_iounmap(a) __iop3xx_iounmap(a) + +#endif diff --git a/arch/arm/mach-iop33x/include/mach/iop33x.h b/arch/arm/mach-iop33x/include/mach/iop33x.h new file mode 100644 index 000000000000..24567316ec88 --- /dev/null +++ b/arch/arm/mach-iop33x/include/mach/iop33x.h @@ -0,0 +1,43 @@ +/* + * arch/arm/mach-iop33x/include/mach/iop33x.h + * + * Intel IOP33X Chip definitions + * + * Author: Dave Jiang (dave.jiang@intel.com) + * Copyright (C) 2003, 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __IOP33X_H +#define __IOP33X_H + +/* + * Peripherals that are shared between the iop32x and iop33x but + * located at different addresses. + */ +#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1780 + (reg)) +#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg)) + +#include <asm/hardware/iop3xx.h> + +/* UARTs */ +#define IOP33X_UART0_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1700) +#define IOP33X_UART0_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1700) +#define IOP33X_UART1_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740) +#define IOP33X_UART1_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740) + +/* ATU Parameters + * set up a 1:1 bus to physical ram relationship + * w/ pci on top of physical ram in memory map + */ +#define IOP33X_MAX_RAM_SIZE 0x80000000UL +#define IOP3XX_MAX_RAM_SIZE IOP33X_MAX_RAM_SIZE +#define IOP3XX_PCI_LOWER_MEM_BA (PHYS_OFFSET + IOP33X_MAX_RAM_SIZE) +#define IOP33X_PCI_MEM_WINDOW_SIZE 0x08000000 +#define IOP3XX_PCI_MEM_WINDOW_SIZE IOP33X_PCI_MEM_WINDOW_SIZE + + +#endif diff --git a/arch/arm/mach-iop33x/include/mach/iq80331.h b/arch/arm/mach-iop33x/include/mach/iq80331.h new file mode 100644 index 000000000000..fe406b0127f7 --- /dev/null +++ b/arch/arm/mach-iop33x/include/mach/iq80331.h @@ -0,0 +1,16 @@ +/* + * arch/arm/mach-iop33x/include/mach/iq80331.h + * + * Intel IQ80331 evaluation board registers + */ + +#ifndef __IQ80331_H +#define __IQ80331_H + +#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */ +#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ +#define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */ +#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */ + + +#endif diff --git a/arch/arm/mach-iop33x/include/mach/iq80332.h b/arch/arm/mach-iop33x/include/mach/iq80332.h new file mode 100644 index 000000000000..8325d71f2ed5 --- /dev/null +++ b/arch/arm/mach-iop33x/include/mach/iq80332.h @@ -0,0 +1,16 @@ +/* + * arch/arm/mach-iop33x/include/mach/iq80332.h + * + * Intel IQ80332 evaluation board registers + */ + +#ifndef __IQ80332_H +#define __IQ80332_H + +#define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */ +#define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ +#define IQ80332_ROTARY_SW 0xce8d0000 /* Rotary Switch */ +#define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */ + + +#endif diff --git a/arch/arm/mach-iop33x/include/mach/irqs.h b/arch/arm/mach-iop33x/include/mach/irqs.h new file mode 100644 index 000000000000..707628a600ac --- /dev/null +++ b/arch/arm/mach-iop33x/include/mach/irqs.h @@ -0,0 +1,60 @@ +/* + * arch/arm/mach-iop33x/include/mach/irqs.h + * + * Author: Dave Jiang (dave.jiang@intel.com) + * Copyright: (C) 2003 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __IRQS_H +#define __IRQS_H + +/* + * IOP80331 chipset interrupts + */ +#define IRQ_IOP33X_DMA0_EOT 0 +#define IRQ_IOP33X_DMA0_EOC 1 +#define IRQ_IOP33X_DMA1_EOT 2 +#define IRQ_IOP33X_DMA1_EOC 3 +#define IRQ_IOP33X_AA_EOT 6 +#define IRQ_IOP33X_AA_EOC 7 +#define IRQ_IOP33X_TIMER0 8 +#define IRQ_IOP33X_TIMER1 9 +#define IRQ_IOP33X_I2C_0 10 +#define IRQ_IOP33X_I2C_1 11 +#define IRQ_IOP33X_MSG 12 +#define IRQ_IOP33X_MSGIBQ 13 +#define IRQ_IOP33X_ATU_BIST 14 +#define IRQ_IOP33X_PERFMON 15 +#define IRQ_IOP33X_CORE_PMU 16 +#define IRQ_IOP33X_XINT0 24 +#define IRQ_IOP33X_XINT1 25 +#define IRQ_IOP33X_XINT2 26 +#define IRQ_IOP33X_XINT3 27 +#define IRQ_IOP33X_XINT8 32 +#define IRQ_IOP33X_XINT9 33 +#define IRQ_IOP33X_XINT10 34 +#define IRQ_IOP33X_XINT11 35 +#define IRQ_IOP33X_XINT12 36 +#define IRQ_IOP33X_XINT13 37 +#define IRQ_IOP33X_XINT14 38 +#define IRQ_IOP33X_XINT15 39 +#define IRQ_IOP33X_UART0 51 +#define IRQ_IOP33X_UART1 52 +#define IRQ_IOP33X_PBIE 53 +#define IRQ_IOP33X_ATU_CRW 54 +#define IRQ_IOP33X_ATU_ERR 55 +#define IRQ_IOP33X_MCU_ERR 56 +#define IRQ_IOP33X_DMA0_ERR 57 +#define IRQ_IOP33X_DMA1_ERR 58 +#define IRQ_IOP33X_AA_ERR 60 +#define IRQ_IOP33X_MSG_ERR 62 +#define IRQ_IOP33X_HPI 63 + +#define NR_IRQS 64 + + +#endif diff --git a/arch/arm/mach-iop33x/include/mach/memory.h b/arch/arm/mach-iop33x/include/mach/memory.h new file mode 100644 index 000000000000..2cef0bbb354f --- /dev/null +++ b/arch/arm/mach-iop33x/include/mach/memory.h @@ -0,0 +1,26 @@ +/* + * arch/arm/mach-iop33x/include/mach/memory.h + */ + +#ifndef __MEMORY_H +#define __MEMORY_H + +#include <mach/hardware.h> + +/* + * Physical DRAM offset. + */ +#define PHYS_OFFSET UL(0x00000000) + +/* + * Virtual view <-> PCI DMA view memory address translations + * virt_to_bus: Used to translate the virtual address to an + * address suitable to be passed to set_dma_addr + * bus_to_virt: Used to convert an address for DMA operations + * to an address that the kernel can use. + */ +#define __virt_to_bus(x) (__virt_to_phys(x)) +#define __bus_to_virt(x) (__phys_to_virt(x)) + + +#endif diff --git a/arch/arm/mach-iop33x/include/mach/system.h b/arch/arm/mach-iop33x/include/mach/system.h new file mode 100644 index 000000000000..7bf3bfb49446 --- /dev/null +++ b/arch/arm/mach-iop33x/include/mach/system.h @@ -0,0 +1,22 @@ +/* + * arch/arm/mach-iop33x/include/mach/system.h + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode) +{ + *IOP3XX_PCSR = 0x30; + + /* Jump into ROM at address 0 */ + cpu_reset(0); +} diff --git a/arch/arm/mach-iop33x/include/mach/time.h b/arch/arm/mach-iop33x/include/mach/time.h new file mode 100644 index 000000000000..4ac4d7664f85 --- /dev/null +++ b/arch/arm/mach-iop33x/include/mach/time.h @@ -0,0 +1,4 @@ +#ifndef _IOP33X_TIME_H_ +#define _IOP33X_TIME_H_ +#define IRQ_IOP_TIMER0 IRQ_IOP33X_TIMER0 +#endif diff --git a/arch/arm/mach-iop33x/include/mach/timex.h b/arch/arm/mach-iop33x/include/mach/timex.h new file mode 100644 index 000000000000..c75760844d49 --- /dev/null +++ b/arch/arm/mach-iop33x/include/mach/timex.h @@ -0,0 +1,9 @@ +/* + * arch/arm/mach-iop33x/include/mach/timex.h + * + * IOP3xx architecture timex specifications + */ + +#include <mach/hardware.h> + +#define CLOCK_TICK_RATE (100 * HZ) diff --git a/arch/arm/mach-iop33x/include/mach/uncompress.h b/arch/arm/mach-iop33x/include/mach/uncompress.h new file mode 100644 index 000000000000..b42423f63302 --- /dev/null +++ b/arch/arm/mach-iop33x/include/mach/uncompress.h @@ -0,0 +1,37 @@ +/* + * arch/arm/mach-iop33x/include/mach/uncompress.h + */ + +#include <asm/types.h> +#include <asm/mach-types.h> +#include <linux/serial_reg.h> +#include <mach/hardware.h> + +static volatile u32 *uart_base; + +#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) + +static inline void putc(char c) +{ + while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE) + barrier(); + uart_base[UART_TX] = c; +} + +static inline void flush(void) +{ +} + +static __inline__ void __arch_decomp_setup(unsigned long arch_id) +{ + if (machine_is_iq80331() || machine_is_iq80332()) + uart_base = (volatile u32 *)IOP33X_UART0_PHYS; + else + uart_base = (volatile u32 *)0xfe800000; +} + +/* + * nothing to do + */ +#define arch_decomp_setup() __arch_decomp_setup(arch_id) +#define arch_decomp_wdog() diff --git a/arch/arm/mach-iop33x/include/mach/vmalloc.h b/arch/arm/mach-iop33x/include/mach/vmalloc.h new file mode 100644 index 000000000000..f9f99dea9bc4 --- /dev/null +++ b/arch/arm/mach-iop33x/include/mach/vmalloc.h @@ -0,0 +1,5 @@ +/* + * arch/arm/mach-iop33x/include/mach/vmalloc.h + */ + +#define VMALLOC_END 0xfe000000 diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c index de39fd778579..c7d99f9fafed 100644 --- a/arch/arm/mach-iop33x/iq80331.c +++ b/arch/arm/mach-iop33x/iq80331.c @@ -22,7 +22,7 @@ #include <linux/serial_8250.h> #include <linux/mtd/physmap.h> #include <linux/platform_device.h> -#include <asm/hardware.h> +#include <mach/hardware.h> #include <asm/io.h> #include <asm/irq.h> #include <asm/mach/arch.h> @@ -32,7 +32,7 @@ #include <asm/mach-types.h> #include <asm/page.h> #include <asm/pgtable.h> -#include <asm/arch/time.h> +#include <mach/time.h> /* * IQ80331 timer tick configuration. diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c index 4904fd78445f..af616c5f4fb2 100644 --- a/arch/arm/mach-iop33x/iq80332.c +++ b/arch/arm/mach-iop33x/iq80332.c @@ -22,7 +22,7 @@ #include <linux/serial_8250.h> #include <linux/mtd/physmap.h> #include <linux/platform_device.h> -#include <asm/hardware.h> +#include <mach/hardware.h> #include <asm/io.h> #include <asm/irq.h> #include <asm/mach/arch.h> @@ -32,7 +32,7 @@ #include <asm/mach-types.h> #include <asm/page.h> #include <asm/pgtable.h> -#include <asm/arch/time.h> +#include <mach/time.h> /* * IQ80332 timer tick configuration. diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c index f09dd054b9c0..abb4ea2ed4fd 100644 --- a/arch/arm/mach-iop33x/irq.c +++ b/arch/arm/mach-iop33x/irq.c @@ -16,7 +16,7 @@ #include <linux/list.h> #include <asm/mach/irq.h> #include <asm/irq.h> -#include <asm/hardware.h> +#include <mach/hardware.h> #include <asm/mach-types.h> static u32 iop33x_mask0; diff --git a/arch/arm/mach-iop33x/uart.c b/arch/arm/mach-iop33x/uart.c index ac297cd0276c..8c21870fa808 100644 --- a/arch/arm/mach-iop33x/uart.c +++ b/arch/arm/mach-iop33x/uart.c @@ -24,9 +24,8 @@ #include <asm/setup.h> #include <asm/system.h> #include <asm/memory.h> -#include <asm/hardware.h> +#include <mach/hardware.h> #include <asm/hardware/iop3xx.h> -#include <asm/mach-types.h> #include <asm/mach/arch.h> #define IOP33X_UART_XTAL 33334000 |
