diff options
Diffstat (limited to 'arch/arm/mach-bcmring/include/mach/csp')
| -rw-r--r-- | arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h | 4 |
3 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h index 70eaea866cfe..161973385faf 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h +++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h @@ -180,7 +180,7 @@ typedef enum { #define chipcHw_XTAL_FREQ_Hz 25000000 /* Reference clock frequency in Hz */ -/* Programable pin defines */ +/* Programmable pin defines */ #define chipcHw_PIN_GPIO(n) ((((n) >= 0) && ((n) < (chipcHw_GPIO_COUNT))) ? (n) : 0xFFFFFFFF) /* GPIO pin 0 - 60 */ #define chipcHw_PIN_UARTTXD (chipcHw_GPIO_COUNT + 0) /* UART Transmit */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h index c78833acb37a..03238c299001 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h +++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h @@ -832,7 +832,7 @@ static inline void chipcHw_setUsbDevice(void) /****************************************************************************/ /** -* @brief Lower layer funtion to enable/disable a clock of a certain device +* @brief Lower layer function to enable/disable a clock of a certain device * * This function enables/disables a core clock * diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h index e01fc4607c91..0aeb6a6fe7f8 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h +++ b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h @@ -109,9 +109,9 @@ #define INTCHW_INTC0_DMA0C0 (1<<INTCHW_INTC0_DMA0C0_BITNUM) /* INTC1 - interrupt controller 1 */ -#define INTCHW_INTC1_DDRVPMP_BITNUM 27 /* DDR and VPM PLL clock phase relationship interupt (Not for A0) */ +#define INTCHW_INTC1_DDRVPMP_BITNUM 27 /* DDR and VPM PLL clock phase relationship interrupt (Not for A0) */ #define INTCHW_INTC1_DDRVPMT_BITNUM 26 /* DDR and VPM HW phase align timeout interrupt (Not for A0) */ -#define INTCHW_INTC1_DDRP_BITNUM 26 /* DDR and PLL clock phase relationship interupt (For A0 only)) */ +#define INTCHW_INTC1_DDRP_BITNUM 26 /* DDR and PLL clock phase relationship interrupt (For A0 only)) */ #define INTCHW_INTC1_RTC2_BITNUM 25 /* Real time clock tamper interrupt */ #define INTCHW_INTC1_VDEC_BITNUM 24 /* Hantro Video Decoder interrupt */ /* Bits 13-23 are non-secure versions of the corresponding secure bits in SINTC bits 0-10. */ |
