diff options
Diffstat (limited to 'Documentation/devicetree/bindings/arm')
76 files changed, 2391 insertions, 1918 deletions
diff --git a/Documentation/devicetree/bindings/arm/actions.txt b/Documentation/devicetree/bindings/arm/actions.txt deleted file mode 100644 index d54f33c4e0da..000000000000 --- a/Documentation/devicetree/bindings/arm/actions.txt +++ /dev/null @@ -1,56 +0,0 @@ -Actions Semi platforms device tree bindings -------------------------------------------- - - -S500 SoC -======== - -Required root node properties: - - - compatible : must contain "actions,s500" - - -Modules: - -Root node property compatible must contain, depending on module: - - - LeMaker Guitar: "lemaker,guitar" - - -Boards: - -Root node property compatible must contain, depending on board: - - - Allo.com Sparky: "allo,sparky" - - Cubietech CubieBoard6: "cubietech,cubieboard6" - - LeMaker Guitar Base Board rev. B: "lemaker,guitar-bb-rev-b", "lemaker,guitar" - - -S700 SoC -======== - -Required root node properties: - -- compatible : must contain "actions,s700" - - -Boards: - -Root node property compatible must contain, depending on board: - - - Cubietech CubieBoard7: "cubietech,cubieboard7" - - -S900 SoC -======== - -Required root node properties: - -- compatible : must contain "actions,s900" - - -Boards: - -Root node property compatible must contain, depending on board: - - - uCRobotics Bubblegum-96: "ucrobotics,bubblegum-96" diff --git a/Documentation/devicetree/bindings/arm/actions.yaml b/Documentation/devicetree/bindings/arm/actions.yaml new file mode 100644 index 000000000000..ace3fdaa8396 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/actions.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/actions.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Actions Semi platforms device tree bindings + +maintainers: + - Andreas Färber <afaerber@suse.de> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +properties: + compatible: + oneOf: + # The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC. + - items: + - enum: + - allo,sparky # Allo.com Sparky + - cubietech,cubieboard6 # Cubietech CubieBoard6 + - const: actions,s500 + - items: + - enum: + - lemaker,guitar-bb-rev-b # LeMaker Guitar Base Board rev. B + - const: lemaker,guitar + - const: actions,s500 + + # The Actions Semi S700 is a quad-core ARM Cortex-A53 SoC. + - items: + - enum: + - cubietech,cubieboard7 # Cubietech CubieBoard7 + - const: actions,s700 + + # The Actions Semi S900 is a quad-core ARM Cortex-A53 SoC. + - items: + - enum: + - ucrobotics,bubblegum-96 # uCRobotics Bubblegum-96 + - const: actions,s900 diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 325c6fd3566d..f74aba48cec1 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -59,6 +59,7 @@ properties: - friendlyarm,nanopi-k2 - hardkernel,odroid-c2 - nexbox,a95x + - videostrong,kii-pro - wetek,hub - wetek,play2 - const: amlogic,meson-gxbb @@ -91,13 +92,11 @@ properties: - description: Boards with the Amlogic Meson GXL S905X SoC items: - enum: - - amediatech,x96-max - amlogic,p212 - hwacom,amazetv - khadas,vim - - libretech,cc + - libretech,aml-s905x-cc - nexbox,a95x - - seirobotics,sei510 - const: amlogic,s905x - const: amlogic,meson-gxl @@ -106,6 +105,7 @@ properties: - enum: - amlogic,p230 - amlogic,p231 + - libretech,aml-s905d-pc - phicomm,n1 - const: amlogic,s905d - const: amlogic,meson-gxl @@ -117,6 +117,7 @@ properties: - amlogic,q201 - khadas,vim2 - kingnovel,r-box-pro + - libretech,aml-s912-pc - nexbox,a1 - tronsmart,vega-s96 - const: amlogic,s912 @@ -129,16 +130,40 @@ properties: - const: amlogic,a113d - const: amlogic,meson-axg - - description: Boards with the Amlogic Meson G12A S905D2 SoC + - description: Boards with the Amlogic Meson G12A S905D2/X2/Y2 SoC items: - enum: + - amediatech,x96-max - amlogic,u200 + - seirobotics,sei510 - const: amlogic,g12a + - description: Boards with the Amlogic Meson G12B A311D SoC + items: + - enum: + - khadas,vim3 + - const: amlogic,a311d + - const: amlogic,g12b + - description: Boards with the Amlogic Meson G12B S922X SoC items: - enum: - hardkernel,odroid-n2 + - khadas,vim3 + - ugoos,am6 + - const: amlogic,s922x - const: amlogic,g12b + - description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC + items: + - enum: + - seirobotics,sei610 + - khadas,vim3l + - const: amlogic,sm1 + + - description: Boards with the Amlogic Meson A1 A113L SoC + items: + - enum: + - amlogic,ad401 + - const: amlogic,a1 ... diff --git a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.txt b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.txt deleted file mode 100644 index c67d9f48fb91..000000000000 --- a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.txt +++ /dev/null @@ -1,28 +0,0 @@ -Amlogic Meson Firmware registers Interface ------------------------------------------- - -The Meson SoCs have a register bank with status and data shared with the -secure firmware. - -Required properties: - - compatible: For Meson GX SoCs, must be "amlogic,meson-gx-ao-secure", "syscon" - -Properties should indentify components of this register interface : - -Meson GX SoC Information ------------------------- -A firmware register encodes the SoC type, package and revision information on -the Meson GX SoCs. -If present, the following property should be added : - -Optional properties: - - amlogic,has-chip-id: If present, the interface gives the current SoC version. - -Example -------- - -ao-secure@140 { - compatible = "amlogic,meson-gx-ao-secure", "syscon"; - reg = <0x0 0x140 0x0 0x140>; - amlogic,has-chip-id; -}; diff --git a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml new file mode 100644 index 000000000000..853d7d2b56f5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 BayLibre, SAS +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-gx-ao-secure.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic Meson Firmware registers Interface + +maintainers: + - Neil Armstrong <narmstrong@baylibre.com> + +description: | + The Meson SoCs have a register bank with status and data shared with the + secure firmware. + +# We need a select here so we don't match all nodes with 'syscon' +select: + properties: + compatible: + contains: + const: amlogic,meson-gx-ao-secure + required: + - compatible + +properties: + compatible: + items: + - const: amlogic,meson-gx-ao-secure + - const: syscon + + reg: + maxItems: 1 + + amlogic,has-chip-id: + description: | + A firmware register encodes the SoC type, package and revision + information on the Meson GX SoCs. If present, the interface gives + the current SoC version. + type: boolean + +required: + - compatible + - reg + +examples: + - | + ao-secure@140 { + compatible = "amlogic,meson-gx-ao-secure", "syscon"; + reg = <0x140 0x140>; + amlogic,has-chip-id; + }; diff --git a/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt b/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt deleted file mode 100644 index 3473ddaadfac..000000000000 --- a/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt +++ /dev/null @@ -1,32 +0,0 @@ -Amlogic Meson8 and Meson8b SRAM for smp bringup: ------------------------------------------------- - -Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores. -Once the core gets powered up it executes the code that is residing at a -specific location. - -Therefore a reserved section sub-node has to be added to the mmio-sram -declaration. - -Required sub-node properties: -- compatible : depending on the SoC this should be one of: - "amlogic,meson8-smp-sram" - "amlogic,meson8b-smp-sram" - -The rest of the properties should follow the generic mmio-sram discription -found in ../../misc/sram.txt - -Example: - - sram: sram@d9000000 { - compatible = "mmio-sram"; - reg = <0xd9000000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xd9000000 0x20000>; - - smp-sram@1ff80 { - compatible = "amlogic,meson8b-smp-sram"; - reg = <0x1ff80 0x8>; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/arm,scmi.txt b/Documentation/devicetree/bindings/arm/arm,scmi.txt index 317a2fc3667a..f493d69e6194 100644 --- a/Documentation/devicetree/bindings/arm/arm,scmi.txt +++ b/Documentation/devicetree/bindings/arm/arm,scmi.txt @@ -73,6 +73,16 @@ Required properties: as used by the firmware. Refer to platform details for your implementation for the IDs to use. +Reset signal bindings for the reset domains based on SCMI Message Protocol +------------------------------------------------------------ + +This binding for the SCMI reset domain providers uses the generic reset +signal binding[5]. + +Required properties: + - #reset-cells : Should be 1. Contains the reset domain ID value used + by SCMI commands. + SRAM and Shared Memory for SCMI ------------------------------- @@ -90,9 +100,10 @@ Required sub-node properties: [0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html [1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/power/power_domain.txt +[2] Documentation/devicetree/bindings/power/power-domain.yaml [3] Documentation/devicetree/bindings/thermal/thermal.txt [4] Documentation/devicetree/bindings/sram/sram.txt +[5] Documentation/devicetree/bindings/reset/reset.txt Example: @@ -152,6 +163,11 @@ firmware { reg = <0x15>; #thermal-sensor-cells = <1>; }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; }; }; @@ -166,6 +182,7 @@ hdlcd@7ff60000 { reg = <0 0x7ff60000 0 0x1000>; clocks = <&scmi_clk 4>; power-domains = <&scmi_devpd 1>; + resets = <&scmi_reset 10>; }; thermal-zones { diff --git a/Documentation/devicetree/bindings/arm/arm,scpi.txt b/Documentation/devicetree/bindings/arm/arm,scpi.txt index 401831973638..7b83ef43b418 100644 --- a/Documentation/devicetree/bindings/arm/arm,scpi.txt +++ b/Documentation/devicetree/bindings/arm/arm,scpi.txt @@ -110,7 +110,7 @@ Required properties: [1] Documentation/devicetree/bindings/clock/clock-bindings.txt [2] Documentation/devicetree/bindings/thermal/thermal.txt [3] Documentation/devicetree/bindings/sram/sram.txt -[4] Documentation/devicetree/bindings/power/power_domain.txt +[4] Documentation/devicetree/bindings/power/power-domain.yaml Example: diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards index 6758ece324b1..96b1dad58253 100644 --- a/Documentation/devicetree/bindings/arm/arm-boards +++ b/Documentation/devicetree/bindings/arm/arm-boards @@ -121,7 +121,7 @@ Required properties (in root node): Required nodes: - soc: some node of the RealView platforms must be the SoC - node that contain the SoC-specific devices, withe the compatible + node that contain the SoC-specific devices, with the compatible string set to one of these tuples: "arm,realview-eb-soc", "simple-bus" "arm,realview-pb1176-soc", "simple-bus" @@ -199,7 +199,7 @@ The description for the board must include: A detailed description of the bindings used for "psci" nodes is present in the psci.yaml file. - a "cpus" node describing the available cores and their associated - "enable-method"s. For more details see cpus.txt file. + "enable-method"s. For more details see cpus.yaml file. Example: diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index 6e168abcd4d1..0357314076bc 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -37,6 +37,16 @@ properties: - items: - enum: + - overkiz,kizboxmini-base # Overkiz kizbox Mini Base Board + - overkiz,kizboxmini-mb # Overkiz kizbox Mini Mother Board + - overkiz,kizboxmini-rd # Overkiz kizbox Mini RailDIN + - overkiz,smartkiz # Overkiz SmartKiz Board + - const: atmel,at91sam9g25 + - const: atmel,at91sam9x5 + - const: atmel,at91sam9 + + - items: + - enum: - atmel,at91sam9g15 - atmel,at91sam9g25 - atmel,at91sam9g35 @@ -45,11 +55,39 @@ properties: - const: atmel,at91sam9x5 - const: atmel,at91sam9 + - description: Overkiz kizbox3 board + items: + - const: overkiz,kizbox3-hs + - const: atmel,sama5d27 + - const: atmel,sama5d2 + - const: atmel,sama5 + + - description: Microchip SAMA5D27 WLSOM1 + items: + - const: microchip,sama5d27-wlsom1 + - const: atmel,sama5d27 + - const: atmel,sama5d2 + - const: atmel,sama5 + + - description: Microchip SAMA5D27 WLSOM1 Evaluation Kit + items: + - const: microchip,sama5d27-wlsom1-ek + - const: microchip,sama5d27-wlsom1 + - const: atmel,sama5d27 + - const: atmel,sama5d2 + - const: atmel,sama5 + - items: - const: atmel,sama5d27 - const: atmel,sama5d2 - const: atmel,sama5 + - description: SAM9X60-EK board + items: + - const: microchip,sam9x60ek + - const: microchip,sam9x60 + - const: atmel,at91sam9 + - description: Nattis v2 board with Natte v2 power board items: - const: axentia,nattis-2 @@ -73,6 +111,13 @@ properties: - const: atmel,sama5d3 - const: atmel,sama5 + - description: Overkiz kizbox2 board with two heads + items: + - const: overkiz,kizbox2-2 + - const: atmel,sama5d31 + - const: atmel,sama5d3 + - const: atmel,sama5 + - items: - enum: - atmel,sama5d31 diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 9fbde401a090..62cd4e89817c 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -10,6 +10,12 @@ PIT Timer required properties: - interrupts: Should contain interrupt for the PIT which is the IRQ line shared across all System Controller members. +PIT64B Timer required properties: +- compatible: Should be "microchip,sam9x60-pit64b" +- reg: Should contain registers location and length +- interrupts: Should contain interrupt for PIT64B timer +- clocks: Should contain the available clock sources for PIT64B timer. + System Timer (ST) required properties: - compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" - reg: Should contain registers location and length @@ -39,6 +45,7 @@ RAMC SDRAM/DDR Controller required properties: "atmel,at91sam9260-sdramc", "atmel,at91sam9g45-ddramc", "atmel,sama5d3-ddramc", + "microchip,sam9x60-ddramc" - reg: Should contain registers location and length Examples: diff --git a/Documentation/devicetree/bindings/arm/axentia.txt b/Documentation/devicetree/bindings/arm/axentia.txt deleted file mode 100644 index de58f2463880..000000000000 --- a/Documentation/devicetree/bindings/arm/axentia.txt +++ /dev/null @@ -1,28 +0,0 @@ -Device tree bindings for Axentia ARM devices -============================================ - -Linea CPU module ----------------- - -Required root node properties: -compatible = "axentia,linea", - "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; -and following the rules from atmel-at91.txt for a sama5d31 SoC. - - -Nattis v2 board with Natte v2 power board ------------------------------------------ - -Required root node properties: -compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea", - "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; -and following the rules from above for the axentia,linea CPU module. - - -TSE-850 v3 board ----------------- - -Required root node properties: -compatible = "axentia,tse850v3", "axentia,linea", - "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; -and following the rules from above for the axentia,linea CPU module. diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml new file mode 100644 index 000000000000..dd52e29b0642 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/bcm2835.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM2711/BCM2835 Platforms Device Tree Bindings + +maintainers: + - Eric Anholt <eric@anholt.net> + - Stefan Wahren <wahrenst@gmx.net> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: BCM2711 based Boards + items: + - enum: + - raspberrypi,4-model-b + - const: brcm,bcm2711 + + - description: BCM2835 based Boards + items: + - enum: + - raspberrypi,model-a + - raspberrypi,model-a-plus + - raspberrypi,model-b + - raspberrypi,model-b-i2c0 # Raspberry Pi Model B (no P5) + - raspberrypi,model-b-rev2 + - raspberrypi,model-b-plus + - raspberrypi,compute-module + - raspberrypi,model-zero + - raspberrypi,model-zero-w + - const: brcm,bcm2835 + + - description: BCM2836 based Boards + items: + - enum: + - raspberrypi,2-model-b + - const: brcm,bcm2836 + + - description: BCM2837 based Boards + items: + - enum: + - raspberrypi,3-model-a-plus + - raspberrypi,3-model-b + - raspberrypi,3-model-b-plus + - raspberrypi,3-compute-module + - raspberrypi,3-compute-module-lite + - const: brcm,bcm2837 + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt deleted file mode 100644 index 245328f36580..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt +++ /dev/null @@ -1,67 +0,0 @@ -Broadcom BCM2835 device tree bindings -------------------------------------------- - -Raspberry Pi Model A -Required root node properties: -compatible = "raspberrypi,model-a", "brcm,bcm2835"; - -Raspberry Pi Model A+ -Required root node properties: -compatible = "raspberrypi,model-a-plus", "brcm,bcm2835"; - -Raspberry Pi Model B -Required root node properties: -compatible = "raspberrypi,model-b", "brcm,bcm2835"; - -Raspberry Pi Model B (no P5) -early model B with I2C0 rather than I2C1 routed to the expansion header -Required root node properties: -compatible = "raspberrypi,model-b-i2c0", "brcm,bcm2835"; - -Raspberry Pi Model B rev2 -Required root node properties: -compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835"; - -Raspberry Pi Model B+ -Required root node properties: -compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; - -Raspberry Pi 2 Model B -Required root node properties: -compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; - -Raspberry Pi 3 Model A+ -Required root node properties: -compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837"; - -Raspberry Pi 3 Model B -Required root node properties: -compatible = "raspberrypi,3-model-b", "brcm,bcm2837"; - -Raspberry Pi 3 Model B+ -Required root node properties: -compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837"; - -Raspberry Pi Compute Module -Required root node properties: -compatible = "raspberrypi,compute-module", "brcm,bcm2835"; - -Raspberry Pi Compute Module 3 -Required root node properties: -compatible = "raspberrypi,3-compute-module", "brcm,bcm2837"; - -Raspberry Pi Compute Module 3 Lite -Required root node properties: -compatible = "raspberrypi,3-compute-module-lite", "brcm,bcm2837"; - -Raspberry Pi Zero -Required root node properties: -compatible = "raspberrypi,model-zero", "brcm,bcm2835"; - -Raspberry Pi Zero W -Required root node properties: -compatible = "raspberrypi,model-zero-w", "brcm,bcm2835"; - -Generic BCM2835 board -Required root node properties: -compatible = "brcm,bcm2835"; diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index fcc3bacfd8bc..d02c42d21f2f 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -87,6 +87,15 @@ its hardware characteristcs. * port or ports: see "Graph bindings for Coresight" below. +* Optional properties for all components: + + * arm,coresight-loses-context-with-cpu : boolean. Indicates that the + hardware will lose register context on CPU power down (e.g. CPUIdle). + An example of where this may be needed are systems which contain a + coresight component and CPU in the same power domain. When the CPU + powers down the coresight component also powers down and loses its + context. This property is currently only used for the ETM 4.x driver. + * Optional properties for ETM/PTMs: * arm,cp14: must be present if the system accesses ETM/PTM management diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index aa40b074b864..7a9c3ce2dbef 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -124,6 +124,7 @@ properties: - arm,cortex-a15 - arm,cortex-a17 - arm,cortex-a53 + - arm,cortex-a55 - arm,cortex-a57 - arm,cortex-a72 - arm,cortex-a73 @@ -155,6 +156,7 @@ properties: - qcom,krait - qcom,kryo - qcom,kryo385 + - qcom,kryo485 - qcom,scorpion enable-method: @@ -175,6 +177,7 @@ properties: - amlogic,meson8-smp - amlogic,meson8b-smp - arm,realview-smp + - aspeed,ast2600-smp - brcm,bcm11351-cpu-method - brcm,bcm23550 - brcm,bcm2836-smp @@ -186,6 +189,7 @@ properties: - marvell,armada-390-smp - marvell,armada-xp-smp - marvell,98dx3236-smp + - marvell,mmp3-smp - mediatek,mt6589-smp - mediatek,mt81xx-tz-smp - qcom,gcc-msm8660 @@ -238,6 +242,21 @@ properties: where voltage is in V, frequency is in MHz. + power-domains: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: + List of phandles and PM domain specifiers, as defined by bindings of the + PM domain provider (see also ../power_domain.txt). + + power-domain-names: + $ref: '/schemas/types.yaml#/definitions/string-array' + description: + A list of power domain name strings sorted in the same order as the + power-domains property. + + For PSCI based platforms, the name corresponding to the index of the PSCI + PM domain provider, must be "psci". + qcom,saw: $ref: '/schemas/types.yaml#/definitions/phandle' description: | diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index a575e42f7fec..e07735a8c2c7 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -124,7 +124,7 @@ Required properties for Pinctrl sub nodes: CONFIG settings. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/power/power_domain.txt +[2] Documentation/devicetree/bindings/power/power-domain.yaml [3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt RTC bindings based on SCU Message Protocol @@ -136,7 +136,9 @@ Required properties: OCOTP bindings based on SCU Message Protocol ------------------------------------------------------------ Required properties: -- compatible: Should be "fsl,imx8qxp-scu-ocotp" +- compatible: Should be one of: + "fsl,imx8qm-scu-ocotp", + "fsl,imx8qxp-scu-ocotp". - #address-cells: Must be 1. Contains byte index - #size-cells: Must be 1. Contains byte length @@ -155,6 +157,15 @@ Required properties: Optional properties: - timeout-sec: contains the watchdog timeout in seconds. +SCU key bindings based on SCU Message Protocol +------------------------------------------------------------ + +Required properties: +- compatible: should be: + "fsl,imx8qxp-sc-key" + followed by "fsl,imx-sc-key"; +- linux,keycodes: See Documentation/devicetree/bindings/input/keys.txt + Example (imx8qxp): ------------- aliases { @@ -218,6 +229,11 @@ firmware { compatible = "fsl,imx8qxp-sc-rtc"; }; + scu_key: scu-key { + compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; + linux,keycodes = <KEY_POWER>; + }; + watchdog { compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; timeout-sec = <60>; diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 7294ac36f4c0..a8e0b4a813ed 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- -$id: http://devicetree.org/schemas/bindings/arm/fsl.yaml# +$id: http://devicetree.org/schemas/arm/fsl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX Platforms Device Tree Bindings @@ -38,12 +38,16 @@ properties: - description: i.MX27 Product Development Kit items: - enum: + - armadeus,imx27-apf27 # APF27 SoM + - armadeus,imx27-apf27dev # APF27 SoM on APF27Dev board - fsl,imx27-pdk - const: fsl,imx27 - description: i.MX28 based Boards items: - enum: + - armadeus,imx28-apf28 # APF28 SoM + - armadeus,imx28-apf28dev # APF28 SoM on APF28Dev board - fsl,imx28-evk - i2se,duckbill - i2se,duckbill-2 @@ -87,7 +91,8 @@ properties: - description: i.MX51 Babbage Board items: - enum: - - armadeus,imx51-apf51 + - armadeus,imx51-apf51 # APF51 SoM + - armadeus,imx51-apf51dev # APF51 SoM on APF51Dev board - fsl,imx51-babbage - technologic,imx51-ts4800 - const: fsl,imx51 @@ -106,6 +111,8 @@ properties: - description: i.MX6Q based Boards items: - enum: + - armadeus,imx6q-apf6 # APF6 (Quad/Dual) SoM + - armadeus,imx6q-apf6dev # APF6 (Quad/Dual) SoM on APF6Dev board - emtrion,emcon-mx6 # emCON-MX6D or emCON-MX6Q SoM - emtrion,emcon-mx6-avari # emCON-MX6D or emCON-MX6Q SoM on Avari Base - fsl,imx6q-arm2 @@ -114,6 +121,32 @@ properties: - fsl,imx6q-sabresd - technologic,imx6q-ts4900 - technologic,imx6q-ts7970 + - toradex,apalis_imx6q # Apalis iMX6 Module + - toradex,apalis_imx6q-eval # Apalis iMX6 Module on Apalis Evaluation Board + - toradex,apalis_imx6q-ixora # Apalis iMX6 Module on Ixora + - toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6 Module on Ixora V1.1 + - variscite,dt6customboard + - const: fsl,imx6q + + - description: i.MX6Q Gateworks Ventana Boards + items: + - enum: + - gw,imx6q-gw51xx + - gw,imx6q-gw52xx + - gw,imx6q-gw53xx + - gw,imx6q-gw5400-a + - gw,imx6q-gw54xx + - gw,imx6q-gw551x + - gw,imx6q-gw552x + - gw,imx6q-gw553x + - gw,imx6q-gw560x + - gw,imx6q-gw5903 + - gw,imx6q-gw5904 + - gw,imx6q-gw5907 + - gw,imx6q-gw5910 + - gw,imx6q-gw5912 + - gw,imx6q-gw5913 + - const: gw,ventana - const: fsl,imx6q - description: i.MX6QP based Boards @@ -126,6 +159,8 @@ properties: - description: i.MX6DL based Boards items: - enum: + - armadeus,imx6dl-apf6 # APF6 (Solo) SoM + - armadeus,imx6dl-apf6dldev # APF6 (Solo) SoM on APF6Dev board - eckelmann,imx6dl-ci4x10 - emtrion,emcon-mx6 # emCON-MX6S or emCON-MX6DL SoM - emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base @@ -133,21 +168,45 @@ properties: - fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board - technologic,imx6dl-ts4900 - technologic,imx6dl-ts7970 + - toradex,colibri_imx6dl # Colibri iMX6 Module + - toradex,colibri_imx6dl-eval-v3 # Colibri iMX6 Module on Colibri Evaluation Board V3 - ysoft,imx6dl-yapp4-draco # i.MX6 DualLite Y Soft IOTA Draco board - ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board - ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board - const: fsl,imx6dl + - description: i.MX6DL Gateworks Ventana Boards + items: + - enum: + - gw,imx6dl-gw51xx + - gw,imx6dl-gw52xx + - gw,imx6dl-gw53xx + - gw,imx6dl-gw54xx + - gw,imx6dl-gw551x + - gw,imx6dl-gw552x + - gw,imx6dl-gw553x + - gw,imx6dl-gw560x + - gw,imx6dl-gw5903 + - gw,imx6dl-gw5904 + - gw,imx6dl-gw5907 + - gw,imx6dl-gw5910 + - gw,imx6dl-gw5912 + - gw,imx6dl-gw5913 + - const: gw,ventana + - const: fsl,imx6dl + - description: i.MX6SL based Boards items: - enum: - fsl,imx6sl-evk # i.MX6 SoloLite EVK Board + - kobo,tolino-shine3 - const: fsl,imx6sl - description: i.MX6SLL based Boards items: - enum: - fsl,imx6sll-evk + - kobo,clarahd - const: fsl,imx6sll - description: i.MX6SX based Boards @@ -155,18 +214,53 @@ properties: - enum: - fsl,imx6sx-sabreauto # i.MX6 SoloX Sabre Auto Board - fsl,imx6sx-sdb # i.MX6 SoloX SDB Board + - fsl,imx6sx-sdb-reva # i.MX6 SoloX SDB Rev-A Board - const: fsl,imx6sx - description: i.MX6UL based Boards items: - enum: + - armadeus,imx6ul-opos6ul # OPOS6UL (i.MX6UL) SoM + - armadeus,imx6ul-opos6uldev # OPOS6UL (i.MX6UL) SoM on OPOS6ULDev board - fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board + - kontron,imx6ul-n6310-som # Kontron N6310 SOM + - kontron,imx6ul-n6311-som # Kontron N6311 SOM + - const: fsl,imx6ul + + - description: Kontron N6310 S Board + items: + - const: kontron,imx6ul-n6310-s + - const: kontron,imx6ul-n6310-som + - const: fsl,imx6ul + + - description: Kontron N6311 S Board + items: + - const: kontron,imx6ul-n6311-s + - const: kontron,imx6ul-n6311-som + - const: fsl,imx6ul + + - description: Kontron N6310 S 43 Board + items: + - const: kontron,imx6ul-n6310-s-43 + - const: kontron,imx6ul-n6310-s + - const: kontron,imx6ul-n6310-som - const: fsl,imx6ul - description: i.MX6ULL based Boards items: - enum: + - armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM + - armadeus,imx6ull-opos6uldev # OPOS6UL (i.MX6ULL) SoM on OPOS6ULDev board - fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board + - kontron,imx6ull-n6411-som # Kontron N6411 SOM + - toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board + - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / Bluetooth Module on Colibri Evaluation Board + - const: fsl,imx6ull + + - description: Kontron N6411 S Board + items: + - const: kontron,imx6ull-n6411-s + - const: kontron,imx6ull-n6411-som - const: fsl,imx6ull - description: i.MX6ULZ based Boards @@ -179,6 +273,8 @@ properties: - description: i.MX7S based Boards items: - enum: + - toradex,colibri-imx7s # Colibri iMX7 Solo Module + - toradex,colibri-imx7s-eval-v3 # Colibri iMX7 Solo Module on Colibri Evaluation Board V3 - tq,imx7s-mba7 # i.MX7S TQ MBa7 with TQMa7S SoM - const: fsl,imx7s @@ -186,8 +282,14 @@ properties: items: - enum: - fsl,imx7d-sdb # i.MX7 SabreSD Board + - fsl,imx7d-sdb-reva # i.MX7 SabreSD Rev-A Board - novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board + - toradex,colibri-imx7d # Colibri iMX7 Dual Module + - toradex,colibri-imx7d-emmc # Colibri iMX7 Dual 1GB (eMMC) Module + - toradex,colibri-imx7d-emmc-eval-v3 # Colibri iMX7 Dual 1GB (eMMC) Module on Colibri Evaluation Board V3 + - toradex,colibri-imx7d-eval-v3 # Colibri iMX7 Dual Module on Colibri Evaluation Board V3 - tq,imx7d-mba7 # i.MX7D TQ MBa7 with TQMa7D SoM + - zii,imx7d-rmu2 # ZII RMU2 Board - zii,imx7d-rpu2 # ZII RPU2 Board - const: fsl,imx7d @@ -205,6 +307,7 @@ properties: - description: i.MX7ULP based Boards items: - enum: + - ea,imx7ulp-com # i.MX7ULP Embedded Artists COM Board - fsl,imx7ulp-evk # i.MX7ULP Evaluation Kit - const: fsl,imx7ulp @@ -214,17 +317,32 @@ properties: - fsl,imx8mm-evk # i.MX8MM EVK Board - const: fsl,imx8mm + - description: i.MX8MN based Boards + items: + - enum: + - fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board + - fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board + - const: fsl,imx8mn + - description: i.MX8MQ based Boards items: - enum: + - boundary,imx8mq-nitrogen8m # i.MX8MQ NITROGEN Board + - einfochips,imx8mq-thor96 # i.MX8MQ Thor96 Board - fsl,imx8mq-evk # i.MX8MQ EVK Board + - google,imx8mq-phanbell # Google Coral Edge TPU - purism,librem5-devkit # Purism Librem5 devkit + - solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse + - technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk - const: fsl,imx8mq - description: i.MX8QXP based Boards items: - enum: + - einfochips,imx8qxp-ai_ml # i.MX8QXP AI_ML Board - fsl,imx8qxp-mek # i.MX8QXP MEK Board + - toradex,colibri-imx8x # Colibri iMX8X Module + - toradex,colibri-imx8x-eval-v3 # Colibri iMX8X Module on Colibri Evaluation Board V3 - const: fsl,imx8qxp - description: @@ -242,6 +360,10 @@ properties: - fsl,vf600 - fsl,vf610 - fsl,vf610m4 + - toradex,vf500-colibri_vf50 # Colibri VF50 Module + - toradex,vf500-colibri_vf50-on-eval # Colibri VF50 Module on Colibri Evaluation Board + - toradex,vf610-colibri_vf61 # Colibri VF61 Module + - toradex,vf610-colibri_vf61-on-eval # Colibri VF61 Module on Colibri Evaluation Board - description: ZII's VF610 based Boards items: @@ -283,6 +405,7 @@ properties: - description: LS1046A based Boards items: - enum: + - fsl,ls1046a-frwy - fsl,ls1046a-qds - fsl,ls1046a-rdb - const: fsl,ls1046a @@ -309,4 +432,17 @@ properties: - fsl,ls2088a-rdb - const: fsl,ls2088a + - description: LX2160A based Boards + items: + - enum: + - fsl,lx2160a-qds + - fsl,lx2160a-rdb + - const: fsl,lx2160a + + - description: S32V234 based Boards + items: + - enum: + - fsl,s32v234-evb # S32V234-EVB2 Customer Evaluation Board + - const: fsl,s32v234 + ... diff --git a/Documentation/devicetree/bindings/arm/idle-states.txt b/Documentation/devicetree/bindings/arm/idle-states.txt deleted file mode 100644 index 2d325bed37e5..000000000000 --- a/Documentation/devicetree/bindings/arm/idle-states.txt +++ /dev/null @@ -1,706 +0,0 @@ -========================================== -ARM idle states binding description -========================================== - -========================================== -1 - Introduction -========================================== - -ARM systems contain HW capable of managing power consumption dynamically, -where cores can be put in different low-power states (ranging from simple -wfi to power gating) according to OS PM policies. The CPU states representing -the range of dynamic idle states that a processor can enter at run-time, can be -specified through device tree bindings representing the parameters required -to enter/exit specific idle states on a given processor. - -According to the Server Base System Architecture document (SBSA, [3]), the -power states an ARM CPU can be put into are identified by the following list: - -- Running -- Idle_standby -- Idle_retention -- Sleep -- Off - -The power states described in the SBSA document define the basic CPU states on -top of which ARM platforms implement power management schemes that allow an OS -PM implementation to put the processor in different idle states (which include -states listed above; "off" state is not an idle state since it does not have -wake-up capabilities, hence it is not considered in this document). - -Idle state parameters (eg entry latency) are platform specific and need to be -characterized with bindings that provide the required information to OS PM -code so that it can build the required tables and use them at runtime. - -The device tree binding definition for ARM idle states is the subject of this -document. - -=========================================== -2 - idle-states definitions -=========================================== - -Idle states are characterized for a specific system through a set of -timing and energy related properties, that underline the HW behaviour -triggered upon idle states entry and exit. - -The following diagram depicts the CPU execution phases and related timing -properties required to enter and exit an idle state: - -..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__.. - | | | | | - - |<------ entry ------->| - | latency | - |<- exit ->| - | latency | - |<-------- min-residency -------->| - |<------- wakeup-latency ------->| - - Diagram 1: CPU idle state execution phases - -EXEC: Normal CPU execution. - -PREP: Preparation phase before committing the hardware to idle mode - like cache flushing. This is abortable on pending wake-up - event conditions. The abort latency is assumed to be negligible - (i.e. less than the ENTRY + EXIT duration). If aborted, CPU - goes back to EXEC. This phase is optional. If not abortable, - this should be included in the ENTRY phase instead. - -ENTRY: The hardware is committed to idle mode. This period must run - to completion up to IDLE before anything else can happen. - -IDLE: This is the actual energy-saving idle period. This may last - between 0 and infinite time, until a wake-up event occurs. - -EXIT: Period during which the CPU is brought back to operational - mode (EXEC). - -entry-latency: Worst case latency required to enter the idle state. The -exit-latency may be guaranteed only after entry-latency has passed. - -min-residency: Minimum period, including preparation and entry, for a given -idle state to be worthwhile energywise. - -wakeup-latency: Maximum delay between the signaling of a wake-up event and the -CPU being able to execute normal code again. If not specified, this is assumed -to be entry-latency + exit-latency. - -These timing parameters can be used by an OS in different circumstances. - -An idle CPU requires the expected min-residency time to select the most -appropriate idle state based on the expected expiry time of the next IRQ -(ie wake-up) that causes the CPU to return to the EXEC phase. - -An operating system scheduler may need to compute the shortest wake-up delay -for CPUs in the system by detecting how long will it take to get a CPU out -of an idle state, eg: - -wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0) - -In other words, the scheduler can make its scheduling decision by selecting -(eg waking-up) the CPU with the shortest wake-up latency. -The wake-up latency must take into account the entry latency if that period -has not expired. The abortable nature of the PREP period can be ignored -if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than -the worst case since it depends on the CPU operating conditions, ie caches -state). - -An OS has to reliably probe the wakeup-latency since some devices can enforce -latency constraints guarantees to work properly, so the OS has to detect the -worst case wake-up latency it can incur if a CPU is allowed to enter an -idle state, and possibly to prevent that to guarantee reliable device -functioning. - -The min-residency time parameter deserves further explanation since it is -expressed in time units but must factor in energy consumption coefficients. - -The energy consumption of a cpu when it enters a power state can be roughly -characterised by the following graph: - - | - | - | - e | - n | /--- - e | /------ - r | /------ - g | /----- - y | /------ - | ---- - | /| - | / | - | / | - | / | - | / | - | / | - |/ | - -----|-------+---------------------------------- - 0| 1 time(ms) - - Graph 1: Energy vs time example - -The graph is split in two parts delimited by time 1ms on the X-axis. -The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope -and denotes the energy costs incurred while entering and leaving the idle -state. -The graph curve in the area delimited by X-axis values = {x | x > 1ms } has -shallower slope and essentially represents the energy consumption of the idle -state. - -min-residency is defined for a given idle state as the minimum expected -residency time for a state (inclusive of preparation and entry) after -which choosing that state become the most energy efficient option. A good -way to visualise this, is by taking the same graph above and comparing some -states energy consumptions plots. - -For sake of simplicity, let's consider a system with two idle states IDLE1, -and IDLE2: - - | - | - | - | /-- IDLE1 - e | /--- - n | /---- - e | /--- - r | /-----/--------- IDLE2 - g | /-------/--------- - y | ------------ /---| - | / /---- | - | / /--- | - | / /---- | - | / /--- | - | --- | - | / | - | / | - |/ | time - ---/----------------------------+------------------------ - |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy - | - IDLE2-min-residency - - Graph 2: idle states min-residency example - -In graph 2 above, that takes into account idle states entry/exit energy -costs, it is clear that if the idle state residency time (ie time till next -wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state -choice energywise. - -This is mainly down to the fact that IDLE1 entry/exit energy costs are lower -than IDLE2. - -However, the lower power consumption (ie shallower energy curve slope) of idle -state IDLE2 implies that after a suitable time, IDLE2 becomes more energy -efficient. - -The time at which IDLE2 becomes more energy efficient than IDLE1 (and other -shallower states in a system with multiple idle states) is defined -IDLE2-min-residency and corresponds to the time when energy consumption of -IDLE1 and IDLE2 states breaks even. - -The definitions provided in this section underpin the idle states -properties specification that is the subject of the following sections. - -=========================================== -3 - idle-states node -=========================================== - -ARM processor idle states are defined within the idle-states node, which is -a direct child of the cpus node [1] and provides a container where the -processor idle states, defined as device tree nodes, are listed. - -- idle-states node - - Usage: Optional - On ARM systems, it is a container of processor idle - states nodes. If the system does not provide CPU - power management capabilities or the processor just - supports idle_standby an idle-states node is not - required. - - Description: idle-states node is a container node, where its - subnodes describe the CPU idle states. - - Node name must be "idle-states". - - The idle-states node's parent node must be the cpus node. - - The idle-states node's child nodes can be: - - - one or more state nodes - - Any other configuration is considered invalid. - - An idle-states node defines the following properties: - - - entry-method - Value type: <stringlist> - Usage and definition depend on ARM architecture version. - # On ARM v8 64-bit this property is required and must - be: - - "psci" - # On ARM 32-bit systems this property is optional - -This assumes that the "enable-method" property is set to "psci" in the cpu -node[6] that is responsible for setting up CPU idle management in the OS -implementation. - -The nodes describing the idle states (state) can only be defined -within the idle-states node, any other configuration is considered invalid -and therefore must be ignored. - -=========================================== -4 - state node -=========================================== - -A state node represents an idle state description and must be defined as -follows: - -- state node - - Description: must be child of the idle-states node - - The state node name shall follow standard device tree naming - rules ([5], 2.2.1 "Node names"), in particular state nodes which - are siblings within a single common parent must be given a unique name. - - The idle state entered by executing the wfi instruction (idle_standby - SBSA,[3][4]) is considered standard on all ARM platforms and therefore - must not be listed. - - With the definitions provided above, the following list represents - the valid properties for a state node: - - - compatible - Usage: Required - Value type: <stringlist> - Definition: Must be "arm,idle-state". - - - local-timer-stop - Usage: See definition - Value type: <none> - Definition: if present the CPU local timer control logic is - lost on state entry, otherwise it is retained. - - - entry-latency-us - Usage: Required - Value type: <prop-encoded-array> - Definition: u32 value representing worst case latency in - microseconds required to enter the idle state. - The exit-latency-us duration may be guaranteed - only after entry-latency-us has passed. - - - exit-latency-us - Usage: Required - Value type: <prop-encoded-array> - Definition: u32 value representing worst case latency - in microseconds required to exit the idle state. - - - min-residency-us - Usage: Required - Value type: <prop-encoded-array> - Definition: u32 value representing minimum residency duration - in microseconds, inclusive of preparation and - entry, for this idle state to be considered - worthwhile energy wise (refer to section 2 of - this document for a complete description). - - - wakeup-latency-us: - Usage: Optional - Value type: <prop-encoded-array> - Definition: u32 value representing maximum delay between the - signaling of a wake-up event and the CPU being - able to execute normal code again. If omitted, - this is assumed to be equal to: - - entry-latency-us + exit-latency-us - - It is important to supply this value on systems - where the duration of PREP phase (see diagram 1, - section 2) is non-neglibigle. - In such systems entry-latency-us + exit-latency-us - will exceed wakeup-latency-us by this duration. - - - status: - Usage: Optional - Value type: <string> - Definition: A standard device tree property [5] that indicates - the operational status of an idle-state. - If present, it shall be: - "okay": to indicate that the idle state is - operational. - "disabled": to indicate that the idle state has - been disabled in firmware so it is not - operational. - If the property is not present the idle-state must - be considered operational. - - - idle-state-name: - Usage: Optional - Value type: <string> - Definition: A string used as a descriptive name for the idle - state. - - In addition to the properties listed above, a state node may require - additional properties specifics to the entry-method defined in the - idle-states node, please refer to the entry-method bindings - documentation for properties definitions. - -=========================================== -4 - Examples -=========================================== - -Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method): - -cpus { - #size-cells = <0>; - #address-cells = <2>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x1>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU4: cpu@10000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10000>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU5: cpu@10001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10001>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU6: cpu@10100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU7: cpu@10101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU8: cpu@100000000 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x0>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - CPU9: cpu@100000001 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x1>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - CPU10: cpu@100000100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - CPU11: cpu@100000101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - CPU12: cpu@100010000 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x10000>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - CPU13: cpu@100010001 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x10001>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - CPU14: cpu@100010100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x10100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - CPU15: cpu@100010101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x10101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - idle-states { - entry-method = "psci"; - - CPU_RETENTION_0_0: cpu-retention-0-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <20>; - exit-latency-us = <40>; - min-residency-us = <80>; - }; - - CLUSTER_RETENTION_0: cluster-retention-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <50>; - exit-latency-us = <100>; - min-residency-us = <250>; - wakeup-latency-us = <130>; - }; - - CPU_SLEEP_0_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <250>; - exit-latency-us = <500>; - min-residency-us = <950>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <600>; - exit-latency-us = <1100>; - min-residency-us = <2700>; - wakeup-latency-us = <1500>; - }; - - CPU_RETENTION_1_0: cpu-retention-1-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <20>; - exit-latency-us = <40>; - min-residency-us = <90>; - }; - - CLUSTER_RETENTION_1: cluster-retention-1 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <50>; - exit-latency-us = <100>; - min-residency-us = <270>; - wakeup-latency-us = <100>; - }; - - CPU_SLEEP_1_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <70>; - exit-latency-us = <100>; - min-residency-us = <300>; - wakeup-latency-us = <150>; - }; - - CLUSTER_SLEEP_1: cluster-sleep-1 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <500>; - exit-latency-us = <1200>; - min-residency-us = <3500>; - wakeup-latency-us = <1300>; - }; - }; - -}; - -Example 2 (ARM 32-bit, 8-cpu system, two clusters): - -cpus { - #size-cells = <0>; - #address-cells = <1>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x2>; - cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x3>; - cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; - }; - - CPU4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>; - }; - - CPU5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>; - }; - - CPU6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>; - }; - - CPU7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>; - }; - - idle-states { - CPU_SLEEP_0_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <200>; - exit-latency-us = <100>; - min-residency-us = <400>; - wakeup-latency-us = <250>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <500>; - exit-latency-us = <1500>; - min-residency-us = <2500>; - wakeup-latency-us = <1700>; - }; - - CPU_SLEEP_1_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <300>; - exit-latency-us = <500>; - min-residency-us = <900>; - wakeup-latency-us = <600>; - }; - - CLUSTER_SLEEP_1: cluster-sleep-1 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <800>; - exit-latency-us = <2000>; - min-residency-us = <6500>; - wakeup-latency-us = <2300>; - }; - }; - -}; - -=========================================== -5 - References -=========================================== - -[1] ARM Linux Kernel documentation - CPUs bindings - Documentation/devicetree/bindings/arm/cpus.yaml - -[2] ARM Linux Kernel documentation - PSCI bindings - Documentation/devicetree/bindings/arm/psci.yaml - -[3] ARM Server Base System Architecture (SBSA) - http://infocenter.arm.com/help/index.jsp - -[4] ARM Architecture Reference Manuals - http://infocenter.arm.com/help/index.jsp - -[5] Devicetree Specification - https://www.devicetree.org/specifications/ - -[6] ARM Linux Kernel documentation - Booting AArch64 Linux - Documentation/arm64/booting.rst diff --git a/Documentation/devicetree/bindings/arm/idle-states.yaml b/Documentation/devicetree/bindings/arm/idle-states.yaml new file mode 100644 index 000000000000..ea805c1e6b20 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/idle-states.yaml @@ -0,0 +1,661 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/idle-states.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM idle states binding description + +maintainers: + - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> + +description: |+ + ========================================== + 1 - Introduction + ========================================== + + ARM systems contain HW capable of managing power consumption dynamically, + where cores can be put in different low-power states (ranging from simple wfi + to power gating) according to OS PM policies. The CPU states representing the + range of dynamic idle states that a processor can enter at run-time, can be + specified through device tree bindings representing the parameters required to + enter/exit specific idle states on a given processor. + + According to the Server Base System Architecture document (SBSA, [3]), the + power states an ARM CPU can be put into are identified by the following list: + + - Running + - Idle_standby + - Idle_retention + - Sleep + - Off + + The power states described in the SBSA document define the basic CPU states on + top of which ARM platforms implement power management schemes that allow an OS + PM implementation to put the processor in different idle states (which include + states listed above; "off" state is not an idle state since it does not have + wake-up capabilities, hence it is not considered in this document). + + Idle state parameters (e.g. entry latency) are platform specific and need to + be characterized with bindings that provide the required information to OS PM + code so that it can build the required tables and use them at runtime. + + The device tree binding definition for ARM idle states is the subject of this + document. + + =========================================== + 2 - idle-states definitions + =========================================== + + Idle states are characterized for a specific system through a set of + timing and energy related properties, that underline the HW behaviour + triggered upon idle states entry and exit. + + The following diagram depicts the CPU execution phases and related timing + properties required to enter and exit an idle state: + + ..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__.. + | | | | | + + |<------ entry ------->| + | latency | + |<- exit ->| + | latency | + |<-------- min-residency -------->| + |<------- wakeup-latency ------->| + + Diagram 1: CPU idle state execution phases + + EXEC: Normal CPU execution. + + PREP: Preparation phase before committing the hardware to idle mode + like cache flushing. This is abortable on pending wake-up + event conditions. The abort latency is assumed to be negligible + (i.e. less than the ENTRY + EXIT duration). If aborted, CPU + goes back to EXEC. This phase is optional. If not abortable, + this should be included in the ENTRY phase instead. + + ENTRY: The hardware is committed to idle mode. This period must run + to completion up to IDLE before anything else can happen. + + IDLE: This is the actual energy-saving idle period. This may last + between 0 and infinite time, until a wake-up event occurs. + + EXIT: Period during which the CPU is brought back to operational + mode (EXEC). + + entry-latency: Worst case latency required to enter the idle state. The + exit-latency may be guaranteed only after entry-latency has passed. + + min-residency: Minimum period, including preparation and entry, for a given + idle state to be worthwhile energywise. + + wakeup-latency: Maximum delay between the signaling of a wake-up event and the + CPU being able to execute normal code again. If not specified, this is assumed + to be entry-latency + exit-latency. + + These timing parameters can be used by an OS in different circumstances. + + An idle CPU requires the expected min-residency time to select the most + appropriate idle state based on the expected expiry time of the next IRQ + (i.e. wake-up) that causes the CPU to return to the EXEC phase. + + An operating system scheduler may need to compute the shortest wake-up delay + for CPUs in the system by detecting how long will it take to get a CPU out + of an idle state, e.g.: + + wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0) + + In other words, the scheduler can make its scheduling decision by selecting + (e.g. waking-up) the CPU with the shortest wake-up delay. + The wake-up delay must take into account the entry latency if that period + has not expired. The abortable nature of the PREP period can be ignored + if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than + the worst case since it depends on the CPU operating conditions, i.e. caches + state). + + An OS has to reliably probe the wakeup-latency since some devices can enforce + latency constraint guarantees to work properly, so the OS has to detect the + worst case wake-up latency it can incur if a CPU is allowed to enter an + idle state, and possibly to prevent that to guarantee reliable device + functioning. + + The min-residency time parameter deserves further explanation since it is + expressed in time units but must factor in energy consumption coefficients. + + The energy consumption of a cpu when it enters a power state can be roughly + characterised by the following graph: + + | + | + | + e | + n | /--- + e | /------ + r | /------ + g | /----- + y | /------ + | ---- + | /| + | / | + | / | + | / | + | / | + | / | + |/ | + -----|-------+---------------------------------- + 0| 1 time(ms) + + Graph 1: Energy vs time example + + The graph is split in two parts delimited by time 1ms on the X-axis. + The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope + and denotes the energy costs incurred while entering and leaving the idle + state. + The graph curve in the area delimited by X-axis values = {x | x > 1ms } has + shallower slope and essentially represents the energy consumption of the idle + state. + + min-residency is defined for a given idle state as the minimum expected + residency time for a state (inclusive of preparation and entry) after + which choosing that state become the most energy efficient option. A good + way to visualise this, is by taking the same graph above and comparing some + states energy consumptions plots. + + For sake of simplicity, let's consider a system with two idle states IDLE1, + and IDLE2: + + | + | + | + | /-- IDLE1 + e | /--- + n | /---- + e | /--- + r | /-----/--------- IDLE2 + g | /-------/--------- + y | ------------ /---| + | / /---- | + | / /--- | + | / /---- | + | / /--- | + | --- | + | / | + | / | + |/ | time + ---/----------------------------+------------------------ + |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy + | + IDLE2-min-residency + + Graph 2: idle states min-residency example + + In graph 2 above, that takes into account idle states entry/exit energy + costs, it is clear that if the idle state residency time (i.e. time till next + wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state + choice energywise. + + This is mainly down to the fact that IDLE1 entry/exit energy costs are lower + than IDLE2. + + However, the lower power consumption (i.e. shallower energy curve slope) of + idle state IDLE2 implies that after a suitable time, IDLE2 becomes more energy + efficient. + + The time at which IDLE2 becomes more energy efficient than IDLE1 (and other + shallower states in a system with multiple idle states) is defined + IDLE2-min-residency and corresponds to the time when energy consumption of + IDLE1 and IDLE2 states breaks even. + + The definitions provided in this section underpin the idle states + properties specification that is the subject of the following sections. + + =========================================== + 3 - idle-states node + =========================================== + + ARM processor idle states are defined within the idle-states node, which is + a direct child of the cpus node [1] and provides a container where the + processor idle states, defined as device tree nodes, are listed. + + On ARM systems, it is a container of processor idle states nodes. If the + system does not provide CPU power management capabilities, or the processor + just supports idle_standby, an idle-states node is not required. + + =========================================== + 4 - References + =========================================== + + [1] ARM Linux Kernel documentation - CPUs bindings + Documentation/devicetree/bindings/arm/cpus.yaml + + [2] ARM Linux Kernel documentation - PSCI bindings + Documentation/devicetree/bindings/arm/psci.yaml + + [3] ARM Server Base System Architecture (SBSA) + http://infocenter.arm.com/help/index.jsp + + [4] ARM Architecture Reference Manuals + http://infocenter.arm.com/help/index.jsp + + [6] ARM Linux Kernel documentation - Booting AArch64 Linux + Documentation/arm64/booting.rst + +properties: + $nodename: + const: idle-states + + entry-method: + description: | + Usage and definition depend on ARM architecture version. + + On ARM v8 64-bit this property is required. + On ARM 32-bit systems this property is optional + + This assumes that the "enable-method" property is set to "psci" in the cpu + node[6] that is responsible for setting up CPU idle management in the OS + implementation. + const: psci + +patternProperties: + "^(cpu|cluster)-": + type: object + description: | + Each state node represents an idle state description and must be defined + as follows. + + The idle state entered by executing the wfi instruction (idle_standby + SBSA,[3][4]) is considered standard on all ARM platforms and therefore + must not be listed. + + In addition to the properties listed above, a state node may require + additional properties specific to the entry-method defined in the + idle-states node. Please refer to the entry-method bindings + documentation for properties definitions. + + properties: + compatible: + const: arm,idle-state + + local-timer-stop: + description: + If present the CPU local timer control logic is + lost on state entry, otherwise it is retained. + type: boolean + + entry-latency-us: + description: + Worst case latency in microseconds required to enter the idle state. + + exit-latency-us: + description: + Worst case latency in microseconds required to exit the idle state. + The exit-latency-us duration may be guaranteed only after + entry-latency-us has passed. + + min-residency-us: + description: + Minimum residency duration in microseconds, inclusive of preparation + and entry, for this idle state to be considered worthwhile energy wise + (refer to section 2 of this document for a complete description). + + wakeup-latency-us: + description: | + Maximum delay between the signaling of a wake-up event and the CPU + being able to execute normal code again. If omitted, this is assumed + to be equal to: + + entry-latency-us + exit-latency-us + + It is important to supply this value on systems where the duration of + PREP phase (see diagram 1, section 2) is non-neglibigle. In such + systems entry-latency-us + exit-latency-us will exceed + wakeup-latency-us by this duration. + + idle-state-name: + $ref: /schemas/types.yaml#definitions/string + description: + A string used as a descriptive name for the idle state. + + required: + - compatible + - entry-latency-us + - exit-latency-us + - min-residency-us + +additionalProperties: false + +examples: + - | + + cpus { + #size-cells = <0>; + #address-cells = <2>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@10000 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10000>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@10001 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10001>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@10100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@10101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + }; + + cpu@100000000 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + cpu@100000001 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + cpu@100000100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + cpu@100000101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + cpu@100010000 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x10000>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + cpu@100010001 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x10001>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + cpu@100010100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x10100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + cpu@100010101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1 0x10101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + }; + + idle-states { + entry-method = "psci"; + + CPU_RETENTION_0_0: cpu-retention-0-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <20>; + exit-latency-us = <40>; + min-residency-us = <80>; + }; + + CLUSTER_RETENTION_0: cluster-retention-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <50>; + exit-latency-us = <100>; + min-residency-us = <250>; + wakeup-latency-us = <130>; + }; + + CPU_SLEEP_0_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <250>; + exit-latency-us = <500>; + min-residency-us = <950>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <600>; + exit-latency-us = <1100>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + + CPU_RETENTION_1_0: cpu-retention-1-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <20>; + exit-latency-us = <40>; + min-residency-us = <90>; + }; + + CLUSTER_RETENTION_1: cluster-retention-1 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <50>; + exit-latency-us = <100>; + min-residency-us = <270>; + wakeup-latency-us = <100>; + }; + + CPU_SLEEP_1_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <70>; + exit-latency-us = <100>; + min-residency-us = <300>; + wakeup-latency-us = <150>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1200>; + min-residency-us = <3500>; + wakeup-latency-us = <1300>; + }; + }; + }; + + - | + // Example 2 (ARM 32-bit, 8-cpu system, two clusters): + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x2>; + cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x3>; + cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>; + }; + + cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>; + }; + + cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>; + }; + + idle-states { + cpu_sleep_0_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <200>; + exit-latency-us = <100>; + min-residency-us = <400>; + wakeup-latency-us = <250>; + }; + + cluster_sleep_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <500>; + exit-latency-us = <1500>; + min-residency-us = <2500>; + wakeup-latency-us = <1700>; + }; + + cpu_sleep_1_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <300>; + exit-latency-us = <500>; + min-residency-us = <900>; + wakeup-latency-us = <600>; + }; + + cluster_sleep_1: cluster-sleep-1 { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <800>; + exit-latency-us = <2000>; + min-residency-us = <6500>; + wakeup-latency-us = <2300>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.yaml b/Documentation/devicetree/bindings/arm/l2c2x0.yaml index bfc5c185561c..913a8cd8b2c0 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.yaml +++ b/Documentation/devicetree/bindings/arm/l2c2x0.yaml @@ -176,6 +176,10 @@ properties: description: disable parity checking on the L2 cache (L220 or PL310). type: boolean + marvell,ecc-enable: + description: enable ECC protection on the L2 cache + type: boolean + arm,outer-sync-disable: description: disable the outer sync operation on the L2 cache. Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that diff --git a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt index 7b8b8eb0191f..098d932fc963 100644 --- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt +++ b/Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt @@ -1,15 +1,15 @@ -Marvell Armada AP806 System Controller +Marvell Armada AP80x System Controller ====================================== -The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K -SoCs. It contains system controllers, which provide several registers -giving access to numerous features: clocks, pin-muxing and many other -SoC configuration items. This DT binding allows to describe these -system controllers. +The AP806/AP807 is one of the two core HW blocks of the Marvell Armada +7K/8K/931x SoCs. It contains system controllers, which provide several +registers giving access to numerous features: clocks, pin-muxing and +many other SoC configuration items. This DT binding allows to describe +these system controllers. For the top level node: - compatible: must be: "syscon", "simple-mfd"; - - reg: register area of the AP806 system controller + - reg: register area of the AP80x system controller SYSTEM CONTROLLER 0 =================== @@ -18,17 +18,19 @@ Clocks: ------- -The Device Tree node representing the AP806 system controller provides -a number of clocks: +The Device Tree node representing the AP806/AP807 system controller +provides a number of clocks: - - 0: clock of CPU cluster 0 - - 1: clock of CPU cluster 1 + - 0: reference clock of CPU cluster 0 + - 1: reference clock of CPU cluster 1 - 2: fixed PLL at 1200 Mhz - 3: MSS clock, derived from the fixed PLL Required properties: - - compatible: must be: "marvell,ap806-clock" + - compatible: must be one of: + * "marvell,ap806-clock" + * "marvell,ap807-clock" - #clock-cells: must be set to 1 Pinctrl: @@ -143,3 +145,33 @@ ap_syscon1: system-controller@6f8000 { #thermal-sensor-cells = <1>; }; }; + +Cluster clocks: +--------------- + +Device Tree Clock bindings for cluster clock of Marvell +AP806/AP807. Each cluster contain up to 2 CPUs running at the same +frequency. + +Required properties: + - compatible: must be one of: + * "marvell,ap806-cpu-clock" + * "marvell,ap807-cpu-clock" +- #clock-cells : should be set to 1. + +- clocks : shall be the input parent clock(s) phandle for the clock + (one per cluster) + +- reg: register range associated with the cluster clocks + +ap_syscon1: system-controller@6f8000 { + compatible = "marvell,armada-ap806-syscon1", "syscon", "simple-mfd"; + reg = <0x6f8000 0x1000>; + + cpu_clk: clock-cpu@278 { + compatible = "marvell,ap806-cpu-clock"; + clocks = <&ap_clk 0>, <&ap_clk 1>; + #clock-cells = <1>; + reg = <0x278 0xa30>; + }; +}; diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt index eddde4faef01..f6d6642d81c0 100644 --- a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt +++ b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt @@ -48,3 +48,11 @@ avs: avs@11500 { compatible = "marvell,armada-3700-avs", "syscon"; reg = <0x11500 0x40>; } + + +CZ.NIC's Turris Mox SOHO router Device Tree Bindings +---------------------------------------------------- + +Required root node property: + + - compatible: must contain "cznic,turris-mox" diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.txt b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.txt deleted file mode 100644 index df98a9c82a8c..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.txt +++ /dev/null @@ -1,24 +0,0 @@ -Marvell Armada 7K/8K Platforms Device Tree Bindings ---------------------------------------------------- - -Boards using a SoC of the Marvell Armada 7K or 8K families must carry -the following root node property: - - - compatible, with one of the following values: - - - "marvell,armada7020", "marvell,armada-ap806-dual", "marvell,armada-ap806" - when the SoC being used is the Armada 7020 - - - "marvell,armada7040", "marvell,armada-ap806-quad", "marvell,armada-ap806" - when the SoC being used is the Armada 7040 - - - "marvell,armada8020", "marvell,armada-ap806-dual", "marvell,armada-ap806" - when the SoC being used is the Armada 8020 - - - "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806" - when the SoC being used is the Armada 8040 - -Example: - -compatible = "marvell,armada7040-db", "marvell,armada7040", - "marvell,armada-ap806-quad", "marvell,armada-ap806"; diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml new file mode 100644 index 000000000000..a9828c50c0fb --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR X11) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/armada-7k-8k.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 7K/8K Platforms Device Tree Bindings + +maintainers: + - Gregory CLEMENT <gregory.clement@bootlin.com> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: Armada 7020 SoC + items: + - const: marvell,armada7020 + - const: marvell,armada-ap806-dual + - const: marvell,armada-ap806 + + - description: Armada 7040 SoC + items: + - const: marvell,armada7040 + - const: marvell,armada-ap806-quad + - const: marvell,armada-ap806 + + - description: Armada 8020 SoC + items: + - const: marvell,armada8020 + - const: marvell,armada-ap806-dual + - const: marvell,armada-ap806 + + - description: Armada 8040 SoC + items: + - const: marvell,armada8040 + - const: marvell,armada-ap806-quad + - const: marvell,armada-ap806 + + - description: Armada CN9130 SoC with no external CP + items: + - const: marvell,cn9130 + - const: marvell,armada-ap807-quad + - const: marvell,armada-ap807 + + - description: Armada CN9131 SoC with one external CP + items: + - const: marvell,cn9131 + - const: marvell,cn9130 + - const: marvell,armada-ap807-quad + - const: marvell,armada-ap807 + + - description: Armada CN9132 SoC with two external CPs + items: + - const: marvell,cn9132 + - const: marvell,cn9131 + - const: marvell,cn9130 + - const: marvell,armada-ap807-quad + - const: marvell,armada-ap807 diff --git a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt index 4db4119a6d19..f982a8ed9396 100644 --- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt +++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt @@ -78,8 +78,8 @@ Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt. Required properties: -- compatible: "marvell,armada-7k-pinctrl", - "marvell,armada-8k-cpm-pinctrl" or "marvell,armada-8k-cps-pinctrl" +- compatible: "marvell,armada-7k-pinctrl", "marvell,armada-8k-cpm-pinctrl", + "marvell,armada-8k-cps-pinctrl" or "marvell,cp115-standalone-pinctrl" depending on the specific variant of the SoC being used. Available mpp pins/groups and functions: diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index a4ad2eb926f9..4043c5046441 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -48,6 +48,10 @@ properties: - const: mediatek,mt6765 - items: - enum: + - mediatek,mt6779-evb + - const: mediatek,mt6779 + - items: + - enum: - mediatek,mt6795-evb - const: mediatek,mt6795 - items: diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt index 161e63a6c254..ff000ccade78 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt @@ -8,6 +8,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-apmixedsys" - "mediatek,mt2712-apmixedsys", "syscon" + - "mediatek,mt6779-apmixedsys", "syscon" - "mediatek,mt6797-apmixedsys" - "mediatek,mt7622-apmixedsys" - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt index 07c9d813465c..e4ca7b703123 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-audsys", "syscon" + - "mediatek,mt6779-audio", "syscon" - "mediatek,mt7622-audsys", "syscon" - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon" - "mediatek,mt8183-audiosys", "syscon" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt index d8930f64aa98..1f4aaa15a37e 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt @@ -6,6 +6,7 @@ The MediaTek camsys controller provides various clocks to the system. Required Properties: - compatible: Should be one of: + - "mediatek,mt6779-camsys", "syscon" - "mediatek,mt8183-camsys", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt index e3bc4a1e7a6e..2b693e343c56 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt @@ -8,6 +8,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-imgsys", "syscon" - "mediatek,mt2712-imgsys", "syscon" + - "mediatek,mt6779-imgsys", "syscon" - "mediatek,mt6797-imgsys", "syscon" - "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon" - "mediatek,mt8173-imgsys", "syscon" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt index a90913988d7e..db2f4fd754e7 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt @@ -9,6 +9,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-infracfg", "syscon" - "mediatek,mt2712-infracfg", "syscon" + - "mediatek,mt6779-infracfg_ao", "syscon" - "mediatek,mt6797-infracfg", "syscon" - "mediatek,mt7622-infracfg", "syscon" - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt new file mode 100644 index 000000000000..2ce889b023d9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt @@ -0,0 +1,22 @@ +Mediatek ipesys controller +============================ + +The Mediatek ipesys controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt6779-ipesys", "syscon" +- #clock-cells: Must be 1 + +The ipesys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +ipesys: clock-controller@1b000000 { + compatible = "mediatek,mt6779-ipesys", "syscon"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt index 72787e7dd227..ad5f9d2f6818 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2712-mfgcfg", "syscon" + - "mediatek,mt6779-mfgcfg", "syscon" - "mediatek,mt8183-mfgcfg", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt index 545eab717c96..301eefbe1618 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt @@ -8,6 +8,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-mmsys", "syscon" - "mediatek,mt2712-mmsys", "syscon" + - "mediatek,mt6779-mmsys", "syscon" - "mediatek,mt6797-mmsys", "syscon" - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon" - "mediatek,mt8173-mmsys", "syscon" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt index 4c7e478117a0..ecf027a9003a 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt @@ -14,6 +14,7 @@ Required Properties: - "mediatek,mt7629-pericfg", "syscon" - "mediatek,mt8135-pericfg", "syscon" - "mediatek,mt8173-pericfg", "syscon" + - "mediatek,mt8183-pericfg", "syscon" - #clock-cells: Must be 1 - #reset-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt index f5518f26a914..30cb645c0e54 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt @@ -9,8 +9,6 @@ Required Properties: - "mediatek,mt7622-sgmiisys", "syscon" - "mediatek,mt7629-sgmiisys", "syscon" - #clock-cells: Must be 1 -- mediatek,physpeed: Should be one of "auto", "1000" or "2500" to match up - the capability of the target PHY. The SGMIISYS controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt index a023b8338960..0293d693ce0c 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt @@ -8,6 +8,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-topckgen" - "mediatek,mt2712-topckgen", "syscon" + - "mediatek,mt6779-topckgen", "syscon" - "mediatek,mt6797-topckgen" - "mediatek,mt7622-topckgen" - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt index 57176bb8dbb5..7894558b7a1c 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt @@ -8,6 +8,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-vdecsys", "syscon" - "mediatek,mt2712-vdecsys", "syscon" + - "mediatek,mt6779-vdecsys", "syscon" - "mediatek,mt6797-vdecsys", "syscon" - "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon" - "mediatek,mt8173-vdecsys", "syscon" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt index c9faa6269087..6a6a14e15cd7 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2712-vencsys", "syscon" + - "mediatek,mt6779-vencsys", "syscon" - "mediatek,mt6797-vencsys", "syscon" - "mediatek,mt8173-vencsys", "syscon" - "mediatek,mt8183-vencsys", "syscon" diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt b/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt deleted file mode 100644 index 951687528efb..000000000000 --- a/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt +++ /dev/null @@ -1,14 +0,0 @@ -Marvell Platforms Device Tree Bindings ----------------------------------------------------- - -PXA168 Aspenite Board -Required root node properties: - - compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168"; - -PXA910 DKB Board -Required root node properties: - - compatible = "mrvl,pxa910-dkb"; - -MMP2 Brownstone Board -Required root node properties: - - compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2"; diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml new file mode 100644 index 000000000000..818dfe6de512 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mrvl/mrvl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Platforms Device Tree Bindings + +maintainers: + - Lubomir Rintel <lkundrak@v3.sk> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: PXA168 Aspenite Board + items: + - enum: + - mrvl,pxa168-aspenite + - const: mrvl,pxa168 + - description: PXA910 DKB Board + items: + - enum: + - mrvl,pxa910-dkb + - const: mrvl,pxa910 + - description: MMP2 based boards + items: + - enum: + - mrvl,mmp2-brownstone + - const: mrvl,mmp2 + - description: MMP3 based boards + items: + - const: mrvl,mmp3 +... diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt deleted file mode 100644 index eaee06b2d8f2..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt +++ /dev/null @@ -1,41 +0,0 @@ -== Introduction== - -LLCC (Last Level Cache Controller) provides last level of cache memory in SOC, -that can be shared by multiple clients. Clients here are different cores in the -SOC, the idea is to minimize the local caches at the clients and migrate to -common pool of memory. Cache memory is divided into partitions called slices -which are assigned to clients. Clients can query the slice details, activate -and deactivate them. - -Properties: -- compatible: - Usage: required - Value type: <string> - Definition: must be "qcom,sdm845-llcc" - -- reg: - Usage: required - Value Type: <prop-encoded-array> - Definition: The first element specifies the llcc base start address and - the size of the register region. The second element specifies - the llcc broadcast base address and size of the register region. - -- reg-names: - Usage: required - Value Type: <stringlist> - Definition: Register region names. Must be "llcc_base", "llcc_broadcast_base". - -- interrupts: - Usage: required - Definition: The interrupt is associated with the llcc edac device. - It's used for llcc cache single and double bit error detection - and reporting. - -Example: - - cache-controller@1100000 { - compatible = "qcom,sdm845-llcc"; - reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml new file mode 100644 index 000000000000..79902f470e4b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Last Level Cache Controller + +maintainers: + - Rishabh Bhatnagar <rishabhb@codeaurora.org> + - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> + +description: | + LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, + that can be shared by multiple clients. Clients here are different cores in the + SoC, the idea is to minimize the local caches at the clients and migrate to + common pool of memory. Cache memory is divided into partitions called slices + which are assigned to clients. Clients can query the slice details, activate + and deactivate them. + +properties: + compatible: + enum: + - qcom,sc7180-llcc + - qcom,sdm845-llcc + + reg: + items: + - description: LLCC base register region + - description: LLCC broadcast base register region + + reg-names: + items: + - const: llcc_base + - const: llcc_broadcast_base + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + system-cache-controller@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt index b301f753ed2c..e77635c5422c 100644 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt @@ -43,7 +43,7 @@ SoC Families: - OMAP2 generic - defaults to OMAP2420 compatible = "ti,omap2" -- OMAP3 generic - defaults to OMAP3430 +- OMAP3 generic compatible = "ti,omap3" - OMAP4 generic - defaults to OMAP4430 compatible = "ti,omap4" @@ -51,6 +51,8 @@ SoC Families: compatible = "ti,omap5" - DRA7 generic - defaults to DRA742 compatible = "ti,dra7" +- AM33x generic + compatible = "ti,am33xx" - AM43x generic - defaults to AM4372 compatible = "ti,am43" @@ -63,12 +65,14 @@ SoCs: - OMAP3430 compatible = "ti,omap3430", "ti,omap3" + legacy: "ti,omap34xx" - please do not use any more - AM3517 compatible = "ti,am3517", "ti,omap3" - OMAP3630 - compatible = "ti,omap36xx", "ti,omap3" -- AM33xx - compatible = "ti,am33xx", "ti,omap3" + compatible = "ti,omap3630", "ti,omap3" + legacy: "ti,omap36xx" - please do not use any more +- AM335x + compatible = "ti,am33xx" - OMAP4430 compatible = "ti,omap4430", "ti,omap4" @@ -110,19 +114,19 @@ SoCs: - AM4372 compatible = "ti,am4372", "ti,am43" -Boards: +Boards (incomplete list of examples): - OMAP3 BeagleBoard : Low cost community board - compatible = "ti,omap3-beagle", "ti,omap3" + compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3" - OMAP3 Tobi with Overo : Commercial expansion board with daughter board - compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3" + compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3" - OMAP4 SDP : Software Development Board - compatible = "ti,omap4-sdp", "ti,omap4430" + compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4" - OMAP4 PandaBoard : Low cost community board - compatible = "ti,omap4-panda", "ti,omap4430" + compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4" - OMAP4 DuoVero with Parlor : Commercial expansion board with daughter board compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; @@ -134,16 +138,16 @@ Boards: compatible = "variscite,var-dvk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; - OMAP3 EVM : Software Development Board for OMAP35x, AM/DM37x - compatible = "ti,omap3-evm", "ti,omap3" + compatible = "ti,omap3-evm", "ti,omap3630", "ti,omap3" - AM335X EVM : Software Development Board for AM335x - compatible = "ti,am335x-evm", "ti,am33xx", "ti,omap3" + compatible = "ti,am335x-evm", "ti,am33xx" - AM335X Bone : Low cost community board - compatible = "ti,am335x-bone", "ti,am33xx", "ti,omap3" + compatible = "ti,am335x-bone", "ti,am33xx" - AM3359 ICEv2 : Low cost Industrial Communication Engine EVM. - compatible = "ti,am3359-icev2", "ti,am33xx", "ti,omap3" + compatible = "ti,am3359-icev2", "ti,am33xx" - AM335X OrionLXm : Substation Automation Platform compatible = "novatech,am335x-lxm", "ti,am33xx" diff --git a/Documentation/devicetree/bindings/arm/omap/prm-inst.txt b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt new file mode 100644 index 000000000000..fcd3456afbbe --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt @@ -0,0 +1,29 @@ +OMAP PRM instance bindings + +Power and Reset Manager is an IP block on OMAP family of devices which +handle the power domains and their current state, and provide reset +handling for the domains and/or separate IP blocks under the power domain +hierarchy. + +Required properties: +- compatible: Must contain one of the following: + "ti,am3-prm-inst" + "ti,am4-prm-inst" + "ti,omap4-prm-inst" + "ti,omap5-prm-inst" + "ti,dra7-prm-inst" + and additionally must contain: + "ti,omap-prm-inst" +- reg: Contains PRM instance register address range + (base address and length) + +Optional properties: +- #reset-cells: Should be 1 if the PRM instance in question supports resets. + +Example: + +prm_dsp2: prm@1b00 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1b00 0x40>; + #reset-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/psci.yaml b/Documentation/devicetree/bindings/arm/psci.yaml index 7abdf58b335e..8ef85420b2ab 100644 --- a/Documentation/devicetree/bindings/arm/psci.yaml +++ b/Documentation/devicetree/bindings/arm/psci.yaml @@ -102,6 +102,34 @@ properties: [1] Kernel documentation - ARM idle states bindings Documentation/devicetree/bindings/arm/idle-states.txt + "#power-domain-cells": + description: + The number of cells in a PM domain specifier as per binding in [3]. + Must be 0 as to represent a single PM domain. + + ARM systems can have multiple cores, sometimes in an hierarchical + arrangement. This often, but not always, maps directly to the processor + power topology of the system. Individual nodes in a topology have their + own specific power states and can be better represented hierarchically. + + For these cases, the definitions of the idle states for the CPUs and the + CPU topology, must conform to the binding in [3]. The idle states + themselves must conform to the binding in [4] and must specify the + arm,psci-suspend-param property. + + It should also be noted that, in PSCI firmware v1.0 the OS-Initiated + (OSI) CPU suspend mode is introduced. Using a hierarchical representation + helps to implement support for OSI mode and OS implementations may choose + to mandate it. + + [3] Documentation/devicetree/bindings/power/power_domain.txt + [4] Documentation/devicetree/bindings/power/domain-idle-state.txt + + power-domains: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: + List of phandles and PM domain specifiers, as defined by bindings of the + PM domain provider. required: - compatible @@ -160,4 +188,80 @@ examples: cpu_on = <0x95c10002>; cpu_off = <0x95c10001>; }; + + - |+ + + // Case 4: CPUs and CPU idle states described using the hierarchical model. + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + }; + + idle-states { + + CPU_PWRDN: cpu-power-down { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0000001>; + entry-latency-us = <10>; + exit-latency-us = <10>; + min-residency-us = <100>; + }; + + CLUSTER_RET: cluster-retention { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000011>; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + + CLUSTER_PWRDN: cluster-power-down { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000031>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + domain-idle-states = <&CPU_PWRDN>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + domain-idle-states = <&CPU_PWRDN>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: cluster-pd { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; + }; + }; ... diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 54ef6b6b9189..5976c0b16b65 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- -$id: http://devicetree.org/schemas/bindings/arm/qcom.yaml# +$id: http://devicetree.org/schemas/arm/qcom.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: QCOM device tree bindings @@ -24,27 +24,30 @@ description: | The 'SoC' element must be one of the following strings: - apq8016 - apq8074 - apq8084 - apq8096 - msm8916 - msm8974 - msm8992 - msm8994 - msm8996 - mdm9615 - ipq8074 - sdm845 + apq8016 + apq8074 + apq8084 + apq8096 + ipq8074 + mdm9615 + msm8916 + msm8974 + msm8992 + msm8994 + msm8996 + sc7180 + sdm845 The 'board' element must be one of the following strings: - cdp - liquid - dragonboard - mtp - sbc - hk01 + cdp + dragonboard + hk01 + idp + liquid + mtp + qrd + sbc The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor> where the minor number may be omitted when it's zero, i.e. v1.0 is the same @@ -116,6 +119,13 @@ properties: - const: qcom,msm8916 - items: + - enum: + - longcheer,l8150 + - samsung,a3u-eur + - samsung,a5u-eur + - const: qcom,msm8916 + + - items: - const: qcom,msm8996-mtp - items: @@ -136,4 +146,8 @@ properties: - qcom,ipq8074-hk01 - const: qcom,ipq8074 + - items: + - enum: + - qcom,sc7180-idp + - const: qcom,sc7180 ... diff --git a/Documentation/devicetree/bindings/arm/realtek.txt b/Documentation/devicetree/bindings/arm/realtek.txt deleted file mode 100644 index 95839e19ae92..000000000000 --- a/Documentation/devicetree/bindings/arm/realtek.txt +++ /dev/null @@ -1,22 +0,0 @@ -Realtek platforms device tree bindings --------------------------------------- - - -RTD1295 SoC -=========== - -Required root node properties: - - - compatible : must contain "realtek,rtd1295" - - -Root node property compatible must contain, depending on board: - - - MeLE V9: "mele,v9" - - ProBox2 AVA: "probox2,ava" - - Zidoo X9S: "zidoo,x9s" - - -Example: - - compatible = "zidoo,x9s", "realtek,rtd1295"; diff --git a/Documentation/devicetree/bindings/arm/realtek.yaml b/Documentation/devicetree/bindings/arm/realtek.yaml new file mode 100644 index 000000000000..ab59de17152d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/realtek.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/realtek.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek platforms device tree bindings + +maintainers: + - Andreas Färber <afaerber@suse.de> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + # RTD1293 SoC based boards + - items: + - enum: + - synology,ds418j # Synology DiskStation DS418j + - const: realtek,rtd1293 + + # RTD1295 SoC based boards + - items: + - enum: + - mele,v9 # MeLE V9 + - probox2,ava # ProBox2 AVA + - zidoo,x9s # Zidoo X9S + - const: realtek,rtd1295 + + # RTD1296 SoC based boards + - items: + - enum: + - synology,ds418 # Synology DiskStation DS418 + - const: realtek,rtd1296 +... diff --git a/Documentation/devicetree/bindings/arm/renesas,prr.txt b/Documentation/devicetree/bindings/arm/renesas,prr.txt deleted file mode 100644 index 08e482e953ca..000000000000 --- a/Documentation/devicetree/bindings/arm/renesas,prr.txt +++ /dev/null @@ -1,20 +0,0 @@ -Renesas Product Register - -Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that -allows to retrieve SoC product and revision information. If present, a device -node for this register should be added. - -Required properties: - - compatible: Must be one of: - "renesas,prr" - "renesas,bsid" - - reg: Base address and length of the register block. - - -Examples --------- - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; diff --git a/Documentation/devicetree/bindings/arm/renesas,prr.yaml b/Documentation/devicetree/bindings/arm/renesas,prr.yaml new file mode 100644 index 000000000000..7f8d17f33983 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/renesas,prr.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/renesas,prr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Product Register + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + - Magnus Damm <magnus.damm@gmail.com> + +description: | + Most Renesas ARM SoCs have a Product Register or Boundary Scan ID + Register that allows to retrieve SoC product and revision information. + If present, a device node for this register should be added. + +properties: + compatible: + enum: + - renesas,prr + - renesas,bsid + reg: + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 28eb458f761a..9436124c5809 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -116,6 +116,18 @@ properties: - const: hoperun,hihope-rzg2m - const: renesas,r8a774a1 + - description: RZ/G2N (R8A774B1) + items: + - enum: + - hoperun,hihope-rzg2n # HopeRun HiHope RZ/G2N platform + - const: renesas,r8a774b1 + + - items: + - enum: + - hoperun,hihope-rzg2-ex # HopeRun expansion board for HiHope RZ/G2 platforms + - const: hoperun,hihope-rzg2n + - const: renesas,r8a774b1 + - description: RZ/G2E (R8A774C0) items: - enum: @@ -193,15 +205,23 @@ properties: - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S) - const: renesas,r8a7796 + - description: R-Car M3-W+ (R8A77961) + items: + - enum: + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012SA5A) + - const: renesas,r8a77961 + - description: Kingfisher (SBEV-RCAR-KF-M03) items: - const: shimafuji,kingfisher - enum: - renesas,h3ulcb - renesas,m3ulcb + - renesas,m3nulcb - enum: - renesas,r8a7795 - renesas,r8a7796 + - renesas,r8a77965 - description: R-Car M3-N (R8A77965) items: diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 34865042f4e4..874b0eaa2a75 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -40,6 +40,11 @@ properties: - const: asus,rk3288-tinker-s - const: rockchip,rk3288 + - description: Beelink A1 + items: + - const: azw,beelink-a1 + - const: rockchip,rk3328 + - description: bq Curie 2 tablet items: - const: mundoreader,bq-curie2 @@ -82,6 +87,11 @@ properties: - const: firefly,firefly-rk3399 - const: rockchip,rk3399 + - description: Firefly ROC-RK3308-CC + items: + - const: firefly,roc-rk3308-cc + - const: rockchip,rk3308 + - description: Firefly roc-rk3328-cc items: - const: firefly,roc-rk3328-cc @@ -89,7 +99,9 @@ properties: - description: Firefly ROC-RK3399-PC items: - - const: firefly,roc-rk3399-pc + - enum: + - firefly,roc-rk3399-pc + - firefly,roc-rk3399-pc-mezzanine - const: rockchip,rk3399 - description: FriendlyElec NanoPi4 series boards @@ -128,6 +140,21 @@ properties: - const: google,veyron - const: rockchip,rk3288 + - description: Google Fievel (AOPEN Chromebox Mini) + items: + - const: google,veyron-fievel-rev8 + - const: google,veyron-fievel-rev7 + - const: google,veyron-fievel-rev6 + - const: google,veyron-fievel-rev5 + - const: google,veyron-fievel-rev4 + - const: google,veyron-fievel-rev3 + - const: google,veyron-fievel-rev2 + - const: google,veyron-fievel-rev1 + - const: google,veyron-fievel-rev0 + - const: google,veyron-fievel + - const: google,veyron + - const: rockchip,rk3288 + - description: Google Gru (dev-board) items: - const: google,gru-rev15 @@ -311,6 +338,21 @@ properties: - const: google,veyron - const: rockchip,rk3288 + - description: Google Tiger (AOpen Chromebase Mini) + items: + - const: google,veyron-tiger-rev8 + - const: google,veyron-tiger-rev7 + - const: google,veyron-tiger-rev6 + - const: google,veyron-tiger-rev5 + - const: google,veyron-tiger-rev4 + - const: google,veyron-tiger-rev3 + - const: google,veyron-tiger-rev2 + - const: google,veyron-tiger-rev1 + - const: google,veyron-tiger-rev0 + - const: google,veyron-tiger + - const: google,veyron + - const: rockchip,rk3288 + - description: Haoyu MarsBoard RK3066 items: - const: haoyu,marsboard-rk3066 @@ -329,6 +371,16 @@ properties: - khadas,edge-v - const: rockchip,rk3399 + - description: Mecer Xtreme Mini S6 + items: + - const: mecer,xms6 + - const: rockchip,rk3229 + + - description: Leez RK3399 P710 + items: + - const: leez,p710 + - const: rockchip,rk3399 + - description: mqmaker MiQi items: - const: mqmaker,miqi @@ -357,6 +409,9 @@ properties: - description: Pine64 RockPro64 items: + - enum: + - pine64,rockpro64-v2.1 + - pine64,rockpro64-v2.0 - const: pine64,rockpro64 - const: rockchip,rk3399 @@ -370,6 +425,12 @@ properties: - const: radxa,rockpi4 - const: rockchip,rk3399 + - description: Radxa ROCK Pi N10 + items: + - const: radxa,rockpi-n10 + - const: vamrs,rk3399pro-vmarc-som + - const: rockchip,rk3399pro + - description: Radxa Rock2 Square items: - const: radxa,rock2-square @@ -424,10 +485,10 @@ properties: - rockchip,rk3288-evb-rk808 - const: rockchip,rk3288 - - description: Rockchip RK3288 Fennec + - description: Rockchip RK3308 Evaluation board items: - - const: rockchip,rk3288-fennec - - const: rockchip,rk3288 + - const: rockchip,rk3308-evb + - const: rockchip,rk3308 - description: Rockchip RK3328 Evaluation board items: @@ -461,12 +522,12 @@ properties: - description: Theobroma Systems RK3368-uQ7 with Haikou baseboard items: - - const: tsd,rk3368-uq7-haikou + - const: tsd,rk3368-lion-haikou - const: rockchip,rk3368 - description: Theobroma Systems RK3399-Q7 with Haikou baseboard items: - - const: tsd,rk3399-q7-haikou + - const: tsd,rk3399-puma-haikou - const: rockchip,rk3399 - description: Tronsmart Orion R68 Meta diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt deleted file mode 100644 index 85c5dfd4a720..000000000000 --- a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt +++ /dev/null @@ -1,12 +0,0 @@ -SAMSUNG Exynos SoCs Chipid driver. - -Required properties: -- compatible : Should at least contain "samsung,exynos4210-chipid". - -- reg: offset and length of the register set - -Example: - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml new file mode 100644 index 000000000000..afcd70803c12 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/samsung/exynos-chipid.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC series Chipid driver + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +properties: + compatible: + items: + - const: samsung,exynos4210-chipid + + reg: + maxItems: 1 + + samsung,asv-bin: + description: + Adaptive Supply Voltage bin selection. This can be used + to determine the ASV bin of an SoC if respective information + is missing in the CHIPID registers or in the OTP memory. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [ 0, 1, 2, 3 ] + +required: + - compatible + - reg + +examples: + - | + chipid@10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + samsung,asv-bin = <2>; + }; diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt deleted file mode 100644 index 433bfd7593ac..000000000000 --- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt +++ /dev/null @@ -1,72 +0,0 @@ -SAMSUNG Exynos SoC series PMU Registers - -Properties: - - compatible : should contain two values. First value must be one from following list: - - "samsung,exynos3250-pmu" - for Exynos3250 SoC, - - "samsung,exynos4210-pmu" - for Exynos4210 SoC, - - "samsung,exynos4412-pmu" - for Exynos4412 SoC, - - "samsung,exynos5250-pmu" - for Exynos5250 SoC, - - "samsung,exynos5260-pmu" - for Exynos5260 SoC. - - "samsung,exynos5410-pmu" - for Exynos5410 SoC, - - "samsung,exynos5420-pmu" - for Exynos5420 SoC. - - "samsung,exynos5433-pmu" - for Exynos5433 SoC. - - "samsung,exynos7-pmu" - for Exynos7 SoC. - second value must be always "syscon". - - - reg : offset and length of the register set. - - - #clock-cells : must be <1>, since PMU requires once cell as clock specifier. - The single specifier cell is used as index to list of clocks - provided by PMU, which is currently: - 0 : SoC clock output (CLKOUT pin) - - - clock-names : list of clock names for particular CLKOUT mux inputs in - following format: - "clkoutN", where N is a decimal number corresponding to - CLKOUT mux control bits value for given input, e.g. - "clkout0", "clkout7", "clkout15". - - - clocks : list of phandles and specifiers to all input clocks listed in - clock-names property. - -Optional properties: - -Some PMUs are capable of behaving as an interrupt controller (mostly -to wake up a suspended PMU). In which case, they can have the -following properties: - -- interrupt-controller: indicate that said PMU is an interrupt controller - -- #interrupt-cells: must be identical to the that of the parent interrupt - controller. - - -Optional nodes: - -- nodes defining the restart and poweroff syscon children - - -Example : -pmu_system_controller: system-controller@10040000 { - compatible = "samsung,exynos5250-pmu", "syscon"; - reg = <0x10040000 0x5000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - #clock-cells = <1>; - clock-names = "clkout0", "clkout1", "clkout2", "clkout3", - "clkout4", "clkout8", "clkout9"; - clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, - <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, - <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, - <&clock CLK_XUSBXTI>; -}; - -Example of clock consumer : - -usb3503: usb3503@8 { - /* ... */ - clock-names = "refclk"; - clocks = <&pmu_system_controller 0>; - /* ... */ -}; diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.yaml b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml new file mode 100644 index 000000000000..73b56fc5bf58 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/samsung/pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC series Power Management Unit (PMU) + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +# Custom select to avoid matching all nodes with 'syscon' +select: + properties: + compatible: + contains: + enum: + - samsung,exynos3250-pmu + - samsung,exynos4210-pmu + - samsung,exynos4412-pmu + - samsung,exynos5250-pmu + - samsung,exynos5260-pmu + - samsung,exynos5410-pmu + - samsung,exynos5420-pmu + - samsung,exynos5433-pmu + - samsung,exynos7-pmu + required: + - compatible + +properties: + compatible: + items: + - enum: + - samsung,exynos3250-pmu + - samsung,exynos4210-pmu + - samsung,exynos4412-pmu + - samsung,exynos5250-pmu + - samsung,exynos5260-pmu + - samsung,exynos5410-pmu + - samsung,exynos5420-pmu + - samsung,exynos5433-pmu + - samsung,exynos7-pmu + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clock-names: + description: + List of clock names for particular CLKOUT mux inputs + minItems: 1 + maxItems: 32 + items: + pattern: '^clkout([0-9]|[12][0-9]|3[0-1])$' + + clocks: + minItems: 1 + maxItems: 32 + + interrupt-controller: + description: + Some PMUs are capable of behaving as an interrupt controller (mostly + to wake up a suspended PMU). + + '#interrupt-cells': + description: + Must be identical to the that of the parent interrupt controller. + const: 3 + + syscon-poweroff: + $ref: "../../power/reset/syscon-poweroff.yaml#" + type: object + description: + Node for power off method + + syscon-reboot: + $ref: "../../power/reset/syscon-reboot.yaml#" + type: object + description: + Node for reboot method + +required: + - compatible + - reg + - '#clock-cells' + - clock-names + - clocks + +examples: + - | + #include <dt-bindings/clock/exynos5250.h> + + pmu_system_controller: system-controller@10040000 { + compatible = "samsung,exynos5250-pmu", "syscon"; + reg = <0x10040000 0x5000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + #clock-cells = <1>; + clock-names = "clkout16"; + clocks = <&clock CLK_FIN_PLL>; + }; diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt deleted file mode 100644 index 56021bf2a916..000000000000 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt +++ /dev/null @@ -1,83 +0,0 @@ -* Samsung's Exynos and S5P SoC based boards - -Required root node properties: - - compatible = should be one or more of the following. - - "samsung,aries" - for S5PV210-based Samsung Aries board. - - "samsung,fascinate4g" - for S5PV210-based Samsung Galaxy S Fascinate 4G (SGH-T959P) board. - - "samsung,galaxys" - for S5PV210-based Samsung Galaxy S (i9000) board. - - "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module. - - "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board. - - "samsung,monk" - for Exynos3250-based Samsung Simband board. - - "samsung,rinato" - for Exynos3250-based Samsung Gear2 board. - - "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board. - - "samsung,trats" - for Exynos4210-based Tizen Reference board. - - "samsung,universal_c210" - for Exynos4210-based Samsung board. - - "samsung,i9300" - for Exynos4412-based Samsung GT-I9300 board. - - "samsung,i9305" - for Exynos4412-based Samsung GT-I9305 board. - - "samsung,midas" - for Exynos4412-based Samsung Midas board. - - "samsung,smdk4412", - for Exynos4412-based Samsung SMDK4412 eval board. - - "samsung,n710x" - for Exynos4412-based Samsung GT-N7100/GT-N7105 board. - - "samsung,trats2" - for Exynos4412-based Tizen Reference board. - - "samsung,smdk5250" - for Exynos5250-based Samsung SMDK5250 eval board. - - "samsung,xyref5260" - for Exynos5260-based Samsung board. - - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board. - - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board. - - "samsung,tm2" - for Exynos5433-based Samsung TM2 board. - - "samsung,tm2e" - for Exynos5433-based Samsung TM2E board. - -* Other companies Exynos SoC based - * FriendlyARM - - "friendlyarm,tiny4412" - for Exynos4412-based FriendlyARM - TINY4412 board. - * TOPEET - - "topeet,itop4412-elite" - for Exynos4412-based TOPEET - Elite base board. - - * Google - - "google,pi" - for Exynos5800-based Google Peach Pi - Rev 10+ board, - also: "google,pi-rev16", "google,pi-rev15", "google,pi-rev14", - "google,pi-rev13", "google,pi-rev12", "google,pi-rev11", - "google,pi-rev10", "google,peach". - - - "google,pit" - for Exynos5420-based Google Peach Pit - Rev 6+ (Exynos5420), - also: "google,pit-rev16", "google,pit-rev15", "google,pit-rev14", - "google,pit-rev13", "google,pit-rev12", "google,pit-rev11", - "google,pit-rev10", "google,pit-rev9", "google,pit-rev8", - "google,pit-rev7", "google,pit-rev6", "google,peach". - - - "google,snow-rev4" - for Exynos5250-based Google Snow board, - also: "google,snow" - - "google,snow-rev5" - for Exynos5250-based Google Snow - Rev 5+ board. - - "google,spring" - for Exynos5250-based Google Spring board. - - * Hardkernel - - "hardkernel,odroid-u3" - for Exynos4412-based Hardkernel Odroid U3. - - "hardkernel,odroid-x" - for Exynos4412-based Hardkernel Odroid X. - - "hardkernel,odroid-x2" - for Exynos4412-based Hardkernel Odroid X2. - - "hardkernel,odroid-xu" - for Exynos5410-based Hardkernel Odroid XU. - - "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3. - - "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel - Odroid XU3 Lite board. - - "hardkernel,odroid-xu4" - for Exynos5422-based Hardkernel Odroid XU4. - - "hardkernel,odroid-hc1" - for Exynos5422-based Hardkernel Odroid HC1. - - * Insignal - - "insignal,arndale" - for Exynos5250-based Insignal Arndale board. - - "insignal,arndale-octa" - for Exynos5420-based Insignal Arndale - Octa board. - - "insignal,origen" - for Exynos4210-based Insignal Origen board. - - "insignal,origen4412" - for Exynos4412-based Insignal Origen board. - - -Optional nodes: - - firmware node, specifying presence and type of secure firmware: - - compatible: only "samsung,secure-firmware" is currently supported - - reg: address of non-secure SYSRAM used for communication with firmware - - firmware@203f000 { - compatible = "samsung,secure-firmware"; - reg = <0x0203F000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml new file mode 100644 index 000000000000..63acd57c4799 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -0,0 +1,181 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/samsung/samsung-boards.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos and S5P SoC based boards + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: S5PV210 based boards + items: + - enum: + - aesop,torbreck # aESOP Torbreck based on S5PV210 + - samsung,aquila # Samsung Aquila based on S5PC110 + - samsung,goni # Samsung Goni based on S5PC110 + - yic,smdkc110 # YIC System SMDKC110 based on S5PC110 + - yic,smdkv210 # YIC System SMDKV210 based on S5PV210 + - const: samsung,s5pv210 + + - description: S5PV210 based Aries boards + items: + - enum: + - samsung,fascinate4g # Samsung Galaxy S Fascinate 4G (SGH-T959P) + - samsung,galaxys # Samsung Galaxy S (i9000) + - const: samsung,aries + - const: samsung,s5pv210 + + - description: Exynos3250 based boards + items: + - enum: + - samsung,monk # Samsung Simband + - samsung,rinato # Samsung Gear2 + - const: samsung,exynos3250 + - const: samsung,exynos3 + + - description: Samsung ARTIK5 boards + items: + - enum: + - samsung,artik5-eval # Samsung ARTIK5 eval board + - const: samsung,artik5 # Samsung ARTIK5 module + - const: samsung,exynos3250 + - const: samsung,exynos3 + + - description: Exynos4210 based boards + items: + - enum: + - insignal,origen # Insignal Origen + - samsung,smdkv310 # Samsung SMDKV310 eval + - samsung,trats # Samsung Tizen Reference + - samsung,universal_c210 # Samsung C210 + - const: samsung,exynos4210 + - const: samsung,exynos4 + + - description: Exynos4412 based boards + items: + - enum: + - friendlyarm,tiny4412 # FriendlyARM TINY4412 + - hardkernel,odroid-u3 # Hardkernel Odroid U3 + - hardkernel,odroid-x # Hardkernel Odroid X + - hardkernel,odroid-x2 # Hardkernel Odroid X2 + - insignal,origen4412 # Insignal Origen + - samsung,smdk4412 # Samsung SMDK4412 eval + - topeet,itop4412-elite # TOPEET Elite base + - const: samsung,exynos4412 + - const: samsung,exynos4 + + - description: Samsung Midas family boards + items: + - enum: + - samsung,i9300 # Samsung GT-I9300 + - samsung,i9305 # Samsung GT-I9305 + - samsung,n710x # Samsung GT-N7100/GT-N7105 + - samsung,trats2 # Samsung Tizen Reference + - const: samsung,midas + - const: samsung,exynos4412 + - const: samsung,exynos4 + + - description: Exynos5250 based boards + items: + - enum: + - google,snow-rev5 # Google Snow Rev 5+ + - google,spring # Google Spring + - insignal,arndale # Insignal Arndale + - samsung,smdk5250 # Samsung SMDK5250 eval + - const: samsung,exynos5250 + - const: samsung,exynos5 + + - description: Google Snow Boards (Rev 4+) + items: + - const: google,snow-rev4 + - const: google,snow + - const: samsung,exynos5250 + - const: samsung,exynos5 + + - description: Exynos5260 based boards + items: + - enum: + - samsung,xyref5260 # Samsung Xyref5260 eval + - const: samsung,exynos5260 + - const: samsung,exynos5 + + - description: Exynos5410 based boards + items: + - enum: + - hardkernel,odroid-xu # Hardkernel Odroid XU + - samsung,smdk5410 # Samsung SMDK5410 eval + - const: samsung,exynos5410 + - const: samsung,exynos5 + + - description: Exynos5420 based boards + items: + - enum: + - insignal,arndale-octa # Insignal Arndale Octa + - samsung,smdk5420 # Samsung SMDK5420 eval + - const: samsung,exynos5420 + - const: samsung,exynos5 + + - description: Google Peach Pit Boards (Rev 6+) + items: + - const: google,pit-rev16 + - const: google,pit-rev15 + - const: google,pit-rev14 + - const: google,pit-rev13 + - const: google,pit-rev12 + - const: google,pit-rev11 + - const: google,pit-rev10 + - const: google,pit-rev9 + - const: google,pit-rev8 + - const: google,pit-rev7 + - const: google,pit-rev6 + - const: google,pit + - const: google,peach + - const: samsung,exynos5420 + - const: samsung,exynos5 + + - description: Exynos5800 based boards + items: + - enum: + - hardkernel,odroid-xu3 # Hardkernel Odroid XU3 + - hardkernel,odroid-xu3-lite # Hardkernel Odroid XU3 Lite + - hardkernel,odroid-xu4 # Hardkernel Odroid XU4 + - hardkernel,odroid-hc1 # Hardkernel Odroid HC1 + - const: samsung,exynos5800 + - const: samsung,exynos5 + + - description: Google Peach Pi Boards (Rev 10+) + items: + - const: google,pi-rev16 + - const: google,pi-rev15 + - const: google,pi-rev14 + - const: google,pi-rev13 + - const: google,pi-rev12 + - const: google,pi-rev11 + - const: google,pi-rev10 + - const: google,pi + - const: google,peach + - const: samsung,exynos5800 + - const: samsung,exynos5 + + - description: Exynos5433 based boards + items: + - enum: + - samsung,tm2 # Samsung TM2 + - samsung,tm2e # Samsung TM2E + - const: samsung,exynos5433 + + - description: Exynos7 based boards + items: + - enum: + - samsung,exynos7-espresso # Samsung Exynos7 Espresso + - const: samsung,exynos7 + +required: + - compatible diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml new file mode 100644 index 000000000000..51d23b6f8a94 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/samsung/samsung-secure-firmware.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos Secure Firmware + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +properties: + compatible: + items: + - const: samsung,secure-firmware + + reg: + description: + Address of non-secure SYSRAM used for communication with firmware. + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + firmware@203f000 { + compatible = "samsung,secure-firmware"; + reg = <0x0203f000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt b/Documentation/devicetree/bindings/arm/samsung/sysreg.txt deleted file mode 100644 index 4fced6e9d5e4..000000000000 --- a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt +++ /dev/null @@ -1,19 +0,0 @@ -SAMSUNG S5P/Exynos SoC series System Registers (SYSREG) - -Properties: - - compatible : should contain two values. First value must be one from following list: - - "samsung,exynos4-sysreg" - for Exynos4 based SoCs, - - "samsung,exynos5-sysreg" - for Exynos5 based SoCs. - second value must be always "syscon". - - reg : offset and length of the register set. - -Example: - syscon@10010000 { - compatible = "samsung,exynos4-sysreg", "syscon"; - reg = <0x10010000 0x400>; - }; - - syscon@10050000 { - compatible = "samsung,exynos5-sysreg", "syscon"; - reg = <0x10050000 0x5000>; - }; diff --git a/Documentation/devicetree/bindings/arm/samsung/sysreg.yaml b/Documentation/devicetree/bindings/arm/samsung/sysreg.yaml new file mode 100644 index 000000000000..3b7811804cb4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/sysreg.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/samsung/sysreg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S5P/Exynos SoC series System Registers (SYSREG) + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +# Custom select to avoid matching all nodes with 'syscon' +select: + properties: + compatible: + contains: + enum: + - samsung,exynos4-sysreg + - samsung,exynos5-sysreg + required: + - compatible + +properties: + compatible: + allOf: + - items: + - enum: + - samsung,exynos4-sysreg + - samsung,exynos5-sysreg + - const: syscon + + reg: + maxItems: 1 + +examples: + - | + syscon@10010000 { + compatible = "samsung,exynos4-sysreg", "syscon"; + reg = <0x10010000 0x400>; + }; + + syscon@10050000 { + compatible = "samsung,exynos5-sysreg", "syscon"; + reg = <0x10050000 0x5000>; + }; diff --git a/Documentation/devicetree/bindings/arm/sprd.txt b/Documentation/devicetree/bindings/arm/sprd.txt deleted file mode 100644 index 3df034b13e28..000000000000 --- a/Documentation/devicetree/bindings/arm/sprd.txt +++ /dev/null @@ -1,14 +0,0 @@ -Spreadtrum SoC Platforms Device Tree Bindings ----------------------------------------------------- - -SC9836 openphone Board -Required root node properties: - - compatible = "sprd,sc9836-openphone", "sprd,sc9836"; - -SC9860 SoC -Required root node properties: - - compatible = "sprd,sc9860" - -SP9860G 3GFHD Board -Required root node properties: - - compatible = "sprd,sp9860g-1h10", "sprd,sc9860"; diff --git a/Documentation/devicetree/bindings/arm/sprd/sprd.yaml b/Documentation/devicetree/bindings/arm/sprd/sprd.yaml new file mode 100644 index 000000000000..0258a96bfbde --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sprd/sprd.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2019 Unisoc Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/sprd/sprd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Unisoc platforms device tree bindings + +maintainers: + - Orson Zhai <orsonzhai@gmail.com> + - Baolin Wang <baolin.wang7@gmail.com> + - Chunyan Zhang <zhang.lyra@gmail.com> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - sprd,sc9836-openphone + - const: sprd,sc9836 + - items: + - enum: + - sprd,sp9860g-1h10 + - const: sprd,sc9860 + - items: + - enum: + - sprd,sp9863a-1h10 + - const: sprd,sc9863a + +... diff --git a/Documentation/devicetree/bindings/arm/stm32/mlahb.txt b/Documentation/devicetree/bindings/arm/stm32/mlahb.txt deleted file mode 100644 index 25307aa1eb9b..000000000000 --- a/Documentation/devicetree/bindings/arm/stm32/mlahb.txt +++ /dev/null @@ -1,37 +0,0 @@ -ML-AHB interconnect bindings - -These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects -a Cortex-M subsystem with dedicated memories. -The MCU SRAM and RETRAM memory parts can be accessed through different addresses -(see "RAM aliases" in [1]) using different buses (see [2]) : balancing the -Cortex-M firmware accesses among those ports allows to tune the system -performance. - -[1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf -[2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping - -Required properties: -- compatible: should be "simple-bus" -- dma-ranges: describes memory addresses translation between the local CPU and - the remote Cortex-M processor. Each memory region, is declared with - 3 parameters: - - param 1: device base address (Cortex-M processor address) - - param 2: physical base address (local CPU address) - - param 3: size of the memory region. - -The Cortex-M remote processor accessed via the mlahb interconnect is described -by a child node. - -Example: -mlahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - dma-ranges = <0x00000000 0x38000000 0x10000>, - <0x10000000 0x10000000 0x60000>, - <0x30000000 0x30000000 0x60000>; - - m4_rproc: m4@10000000 { - ... - }; -}; diff --git a/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml b/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml new file mode 100644 index 000000000000..68917bb7c7e8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/stm32/st,mlahb.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: STMicroelectronics STM32 ML-AHB interconnect bindings + +maintainers: + - Fabien Dessenne <fabien.dessenne@st.com> + - Arnaud Pouliquen <arnaud.pouliquen@st.com> + +description: | + These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects + a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory + parts can be accessed through different addresses (see "RAM aliases" in [1]) + using different buses (see [2]): balancing the Cortex-M firmware accesses + among those ports allows to tune the system performance. + [1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf + [2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping + +allOf: + - $ref: /schemas/simple-bus.yaml# + +properties: + compatible: + contains: + enum: + - st,mlahb + + dma-ranges: + description: | + Describe memory addresses translation between the local CPU and the + remote Cortex-M processor. Each memory region, is declared with + 3 parameters: + - param 1: device base address (Cortex-M processor address) + - param 2: physical base address (local CPU address) + - param 3: size of the memory region. + maxItems: 3 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + +required: + - compatible + - '#address-cells' + - '#size-cells' + - dma-ranges + +examples: + - | + mlahb: ahb { + compatible = "st,mlahb", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x10000000 0x40000>; + ranges; + dma-ranges = <0x00000000 0x38000000 0x10000>, + <0x10000000 0x10000000 0x60000>, + <0x30000000 0x30000000 0x60000>; + + m4_rproc: m4@10000000 { + reg = <0x10000000 0x40000>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml new file mode 100644 index 000000000000..0dedf94c8578 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/stm32/st,stm32-syscon.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: STMicroelectronics STM32 Platforms System Controller bindings + +maintainers: + - Alexandre Torgue <alexandre.torgue@st.com> + - Christophe Roullier <christophe.roullier@st.com> + +properties: + compatible: + oneOf: + - items: + - enum: + - st,stm32mp157-syscfg + - const: syscon + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +examples: + - | + #include <dt-bindings/clock/stm32mp1-clks.h> + syscfg: syscon@50020000 { + compatible = "st,stm32mp157-syscfg", "syscon"; + reg = <0x50020000 0x400>; + clocks = <&rcc SYSCFG>; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt b/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt deleted file mode 100644 index c92d411fd023..000000000000 --- a/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt +++ /dev/null @@ -1,16 +0,0 @@ -STMicroelectronics STM32 Platforms System Controller - -Properties: - - compatible : should contain two values. First value must be : - - " st,stm32mp157-syscfg " - for stm32mp157 based SoCs, - second value must be always "syscon". - - reg : offset and length of the register set. - - clocks: phandle to the syscfg clock - - Example: - syscfg: syscon@50020000 { - compatible = "st,stm32mp157-syscfg", "syscon"; - reg = <0x50020000 0x400>; - clocks = <&rcc SYSCFG>; - }; - diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 4d194f1eb03a..1fcf306bd2d1 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -13,19 +13,38 @@ properties: compatible: oneOf: - items: + - enum: + - st,stm32f429i-disco + - st,stm32429i-eval - const: st,stm32f429 - - items: + - enum: + - st,stm32f469i-disco - const: st,stm32f469 - - items: + - enum: + - st,stm32f746-disco + - st,stm32746g-eval - const: st,stm32f746 - - items: + - enum: + - st,stm32f769-disco + - const: st,stm32f769 + - items: + - enum: + - st,stm32h743i-disco + - st,stm32h743i-eval - const: st,stm32h743 - - items: - enum: - arrow,stm32mp157a-avenger96 # Avenger96 + - st,stm32mp157c-ed1 + - st,stm32mp157a-dk1 + - st,stm32mp157c-dk2 + + - const: st,stm32mp157 + - items: + - const: st,stm32mp157c-ev1 + - const: st,stm32mp157c-ed1 - const: st,stm32mp157 ... diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 000a00d12d6a..327ce6730823 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -8,7 +8,7 @@ title: Allwinner platforms device tree bindings maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: $nodename: @@ -211,6 +211,11 @@ properties: - const: friendlyarm,nanopi-a64 - const: allwinner,sun50i-a64 + - description: FriendlyARM NanoPi Duo2 + items: + - const: friendlyarm,nanopi-duo2 + - const: allwinner,sun8i-h3 + - description: FriendlyARM NanoPi M1 items: - const: friendlyarm,nanopi-m1 @@ -337,6 +342,16 @@ properties: - const: libretech,all-h3-cc-h5 - const: allwinner,sun50i-h5 + - description: Libre Computer Board ALL-H3-IT H5 + items: + - const: libretech,all-h3-it-h5 + - const: allwinner,sun50i-h5 + + - description: Libre Computer Board ALL-H5-CC H5 + items: + - const: libretech,all-h5-cc-h5 + - const: allwinner,sun50i-h5 + - description: Lichee Pi One items: - const: licheepi,licheepi-one @@ -353,6 +368,12 @@ properties: - const: licheepi,licheepi-zero - const: allwinner,sun8i-v3s + - description: Lichee Zero Plus (with S3, without eMMC/SPI Flash) + items: + - const: sipeed,lichee-zero-plus + - const: sochip,s3 + - const: allwinner,sun8i-v3 + - description: Linksprite PCDuino items: - const: linksprite,a10-pcduino @@ -459,6 +480,12 @@ properties: - const: emlid,neutis-n5 - const: allwinner,sun50i-h5 + - description: Emlid Neutis N5H3 Developper Board + items: + - const: emlid,neutis-n5h3-devboard + - const: emlid,neutis-n5h3 + - const: allwinner,sun8i-h3 + - description: NextThing Co. CHIP items: - const: nextthing,chip @@ -568,6 +595,11 @@ properties: - const: olimex,a64-olinuxino - const: allwinner,sun50i-a64 + - description: Olimex A64-OlinuXino (with eMMC) + items: + - const: olimex,a64-olinuxino-emmc + - const: allwinner,sun50i-a64 + - description: Olimex A64 Teres-I items: - const: olimex,a64-teres-i @@ -583,11 +615,16 @@ properties: - const: pine64,pine64-plus - const: allwinner,sun50i-a64 - - description: Pine64 PineH64 + - description: Pine64 PineH64 model A items: - const: pine64,pine-h64 - const: allwinner,sun50i-h6 + - description: Pine64 PineH64 model B + items: + - const: pine64,pine-h64-model-b + - const: allwinner,sun50i-h6 + - description: Pine64 LTS items: - const: pine64,pine64-lts @@ -671,6 +708,11 @@ properties: - const: sinlinx,sina33 - const: allwinner,sun8i-a33 + - description: Tanix TX6 + items: + - const: oranth,tanix-tx6 + - const: allwinner,sun50i-h6 + - description: TBS A711 Tablet items: - const: tbs-biometrics,a711 diff --git a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml new file mode 100644 index 000000000000..9370e64992dd --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner Memory Bus (MBUS) controller + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +description: | + The MBUS controller drives the MBUS that other devices in the SoC + will use to perform DMA. It also has a register interface that + allows to monitor and control the bandwidth and priorities for + masters on that bus. + + Each device having to perform their DMA through the MBUS must have + the interconnects and interconnect-names properties set to the MBUS + controller and with "dma-mem" as the interconnect name. + +properties: + "#interconnect-cells": + const: 1 + description: + The content of the cell is the MBUS ID. + + compatible: + enum: + - allwinner,sun5i-a13-mbus + - allwinner,sun8i-h3-mbus + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + dma-ranges: + description: + See section 2.3.9 of the DeviceTree Specification. + +required: + - "#interconnect-cells" + - compatible + - reg + - clocks + - dma-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun5i-ccu.h> + + mbus: dram-controller@1c01000 { + compatible = "allwinner,sun5i-a13-mbus"; + reg = <0x01c01000 0x1000>; + clocks = <&ccu CLK_MBUS>; + dma-ranges = <0x00000000 0x40000000 0x20000000>; + #interconnect-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt b/Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt deleted file mode 100644 index 082e6a9382d3..000000000000 --- a/Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt +++ /dev/null @@ -1,44 +0,0 @@ -Allwinner SRAM for smp bringup: ------------------------------------------------- - -Allwinner's A80 SoC uses part of the secure sram for hotplugging of the -primary core (cpu0). Once the core gets powered up it checks if a magic -value is set at a specific location. If it is then the BROM will jump -to the software entry address, instead of executing a standard boot. - -Therefore a reserved section sub-node has to be added to the mmio-sram -declaration. - -Note that this is separate from the Allwinner SRAM controller found in -../../sram/sunxi-sram.txt. This SRAM is secure only and not mappable to -any device. - -Also there are no "secure-only" properties. The implementation should -check if this SRAM is usable first. - -Required sub-node properties: -- compatible : depending on the SoC this should be one of: - "allwinner,sun9i-a80-smp-sram" - -The rest of the properties should follow the generic mmio-sram discription -found in ../../misc/sram.txt - -Example: - - sram_b: sram@20000 { - /* 256 KiB secure SRAM at 0x20000 */ - compatible = "mmio-sram"; - reg = <0x00020000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00020000 0x40000>; - - smp-sram@1000 { - /* - * This is checked by BROM to determine if - * cpu0 should jump to SMP entry vector - */ - compatible = "allwinner,sun9i-a80-smp-sram"; - reg = <0x1000 0x8>; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt b/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt deleted file mode 100644 index 1464a4713553..000000000000 --- a/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt +++ /dev/null @@ -1,36 +0,0 @@ -Allwinner Memory Bus (MBUS) controller - -The MBUS controller drives the MBUS that other devices in the SoC will -use to perform DMA. It also has a register interface that allows to -monitor and control the bandwidth and priorities for masters on that -bus. - -Required properties: - - compatible: Must be one of: - - allwinner,sun5i-a13-mbus - - reg: Offset and length of the register set for the controller - - clocks: phandle to the clock driving the controller - - dma-ranges: See section 2.3.9 of the DeviceTree Specification - - #interconnect-cells: Must be one, with the argument being the MBUS - port ID - -Each device having to perform their DMA through the MBUS must have the -interconnects and interconnect-names properties set to the MBUS -controller and with "dma-mem" as the interconnect name. - -Example: - -mbus: dram-controller@1c01000 { - compatible = "allwinner,sun5i-a13-mbus"; - reg = <0x01c01000 0x1000>; - clocks = <&ccu CLK_MBUS>; - dma-ranges = <0x00000000 0x40000000 0x20000000>; - #interconnect-cells = <1>; -}; - -fe0: display-frontend@1e00000 { - compatible = "allwinner,sun5i-a13-display-frontend"; - ... - interconnects = <&mbus 19>; - interconnect-names = "dma-mem"; -}; diff --git a/Documentation/devicetree/bindings/arm/topology.txt b/Documentation/devicetree/bindings/arm/topology.txt deleted file mode 100644 index b0d80c0fb265..000000000000 --- a/Documentation/devicetree/bindings/arm/topology.txt +++ /dev/null @@ -1,475 +0,0 @@ -=========================================== -ARM topology binding description -=========================================== - -=========================================== -1 - Introduction -=========================================== - -In an ARM system, the hierarchy of CPUs is defined through three entities that -are used to describe the layout of physical CPUs in the system: - -- cluster -- core -- thread - -The cpu nodes (bindings defined in [1]) represent the devices that -correspond to physical CPUs and are to be mapped to the hierarchy levels. - -The bottom hierarchy level sits at core or thread level depending on whether -symmetric multi-threading (SMT) is supported or not. - -For instance in a system where CPUs support SMT, "cpu" nodes represent all -threads existing in the system and map to the hierarchy level "thread" above. -In systems where SMT is not supported "cpu" nodes represent all cores present -in the system and map to the hierarchy level "core" above. - -ARM topology bindings allow one to associate cpu nodes with hierarchical groups -corresponding to the system hierarchy; syntactically they are defined as device -tree nodes. - -The remainder of this document provides the topology bindings for ARM, based -on the Devicetree Specification, available from: - -https://www.devicetree.org/specifications/ - -If not stated otherwise, whenever a reference to a cpu node phandle is made its -value must point to a cpu node compliant with the cpu node bindings as -documented in [1]. -A topology description containing phandles to cpu nodes that are not compliant -with bindings standardized in [1] is therefore considered invalid. - -=========================================== -2 - cpu-map node -=========================================== - -The ARM CPU topology is defined within the cpu-map node, which is a direct -child of the cpus node and provides a container where the actual topology -nodes are listed. - -- cpu-map node - - Usage: Optional - On ARM SMP systems provide CPUs topology to the OS. - ARM uniprocessor systems do not require a topology - description and therefore should not define a - cpu-map node. - - Description: The cpu-map node is just a container node where its - subnodes describe the CPU topology. - - Node name must be "cpu-map". - - The cpu-map node's parent node must be the cpus node. - - The cpu-map node's child nodes can be: - - - one or more cluster nodes - - Any other configuration is considered invalid. - -The cpu-map node can only contain three types of child nodes: - -- cluster node -- core node -- thread node - -whose bindings are described in paragraph 3. - -The nodes describing the CPU topology (cluster/core/thread) can only -be defined within the cpu-map node and every core/thread in the system -must be defined within the topology. Any other configuration is -invalid and therefore must be ignored. - -=========================================== -2.1 - cpu-map child nodes naming convention -=========================================== - -cpu-map child nodes must follow a naming convention where the node name -must be "clusterN", "coreN", "threadN" depending on the node type (ie -cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes which -are siblings within a single common parent node must be given a unique and -sequential N value, starting from 0). -cpu-map child nodes which do not share a common parent node can have the same -name (ie same number N as other cpu-map child nodes at different device tree -levels) since name uniqueness will be guaranteed by the device tree hierarchy. - -=========================================== -3 - cluster/core/thread node bindings -=========================================== - -Bindings for cluster/cpu/thread nodes are defined as follows: - -- cluster node - - Description: must be declared within a cpu-map node, one node - per cluster. A system can contain several layers of - clustering and cluster nodes can be contained in parent - cluster nodes. - - The cluster node name must be "clusterN" as described in 2.1 above. - A cluster node can not be a leaf node. - - A cluster node's child nodes must be: - - - one or more cluster nodes; or - - one or more core nodes - - Any other configuration is considered invalid. - -- core node - - Description: must be declared in a cluster node, one node per core in - the cluster. If the system does not support SMT, core - nodes are leaf nodes, otherwise they become containers of - thread nodes. - - The core node name must be "coreN" as described in 2.1 above. - - A core node must be a leaf node if SMT is not supported. - - Properties for core nodes that are leaf nodes: - - - cpu - Usage: required - Value type: <phandle> - Definition: a phandle to the cpu node that corresponds to the - core node. - - If a core node is not a leaf node (CPUs supporting SMT) a core node's - child nodes can be: - - - one or more thread nodes - - Any other configuration is considered invalid. - -- thread node - - Description: must be declared in a core node, one node per thread - in the core if the system supports SMT. Thread nodes are - always leaf nodes in the device tree. - - The thread node name must be "threadN" as described in 2.1 above. - - A thread node must be a leaf node. - - A thread node must contain the following property: - - - cpu - Usage: required - Value type: <phandle> - Definition: a phandle to the cpu node that corresponds to - the thread node. - -=========================================== -4 - Example dts -=========================================== - -Example 1 (ARM 64-bit, 16-cpu system, two clusters of clusters): - -cpus { - #size-cells = <0>; - #address-cells = <2>; - - cpu-map { - cluster0 { - cluster0 { - core0 { - thread0 { - cpu = <&CPU0>; - }; - thread1 { - cpu = <&CPU1>; - }; - }; - - core1 { - thread0 { - cpu = <&CPU2>; - }; - thread1 { - cpu = <&CPU3>; - }; - }; - }; - - cluster1 { - core0 { - thread0 { - cpu = <&CPU4>; - }; - thread1 { - cpu = <&CPU5>; - }; - }; - - core1 { - thread0 { - cpu = <&CPU6>; - }; - thread1 { - cpu = <&CPU7>; - }; - }; - }; - }; - - cluster1 { - cluster0 { - core0 { - thread0 { - cpu = <&CPU8>; - }; - thread1 { - cpu = <&CPU9>; - }; - }; - core1 { - thread0 { - cpu = <&CPU10>; - }; - thread1 { - cpu = <&CPU11>; - }; - }; - }; - - cluster1 { - core0 { - thread0 { - cpu = <&CPU12>; - }; - thread1 { - cpu = <&CPU13>; - }; - }; - core1 { - thread0 { - cpu = <&CPU14>; - }; - thread1 { - cpu = <&CPU15>; - }; - }; - }; - }; - }; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU4: cpu@10000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU5: cpu@10001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU6: cpu@10100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU7: cpu@10101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU8: cpu@100000000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU9: cpu@100000001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU10: cpu@100000100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU11: cpu@100000101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU12: cpu@100010000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU13: cpu@100010001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU14: cpu@100010100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU15: cpu@100010101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; -}; - -Example 2 (ARM 32-bit, dual-cluster, 8-cpu system, no SMT): - -cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - core2 { - cpu = <&CPU2>; - }; - core3 { - cpu = <&CPU3>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU4>; - }; - core1 { - cpu = <&CPU5>; - }; - core2 { - cpu = <&CPU6>; - }; - core3 { - cpu = <&CPU7>; - }; - }; - }; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x2>; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x3>; - }; - - CPU4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - }; - - CPU5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - }; - - CPU6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - }; - - CPU7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - }; -}; - -=============================================================================== -[1] ARM Linux kernel documentation - Documentation/devicetree/bindings/arm/cpus.yaml diff --git a/Documentation/devicetree/bindings/arm/ux500.yaml b/Documentation/devicetree/bindings/arm/ux500.yaml new file mode 100644 index 000000000000..accaee906050 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ux500.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/ux500.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ux500 platforms device tree bindings + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: ST-Ericsson HREF (pre-v60) + items: + - const: st-ericsson,mop500 + - const: st-ericsson,u8500 + + - description: ST-Ericsson HREF (v60+) + items: + - const: st-ericsson,hrefv60+ + - const: st-ericsson,u8500 + + - description: Calao Systems Snowball + items: + - const: calaosystems,snowball-a9500 + - const: st-ericsson,u9500 + + - description: Samsung Galaxy S III mini (GT-I8190) + items: + - const: samsung,golden + - const: st-ericsson,u8500 |
