diff options
| -rw-r--r-- | arch/frv/include/asm/cache.h | 2 | ||||
| -rw-r--r-- | arch/frv/include/asm/mem-layout.h | 4 |
2 files changed, 2 insertions, 4 deletions
diff --git a/arch/frv/include/asm/cache.h b/arch/frv/include/asm/cache.h index 7dc0f0f85b7c..2797163b8f4f 100644 --- a/arch/frv/include/asm/cache.h +++ b/arch/frv/include/asm/cache.h @@ -17,8 +17,6 @@ #define L1_CACHE_SHIFT (CONFIG_FRV_L1_CACHE_SHIFT) #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES - #define __cacheline_aligned __attribute__((aligned(L1_CACHE_BYTES))) #define ____cacheline_aligned __attribute__((aligned(L1_CACHE_BYTES))) diff --git a/arch/frv/include/asm/mem-layout.h b/arch/frv/include/asm/mem-layout.h index 2947764fc0e0..ccae981876fa 100644 --- a/arch/frv/include/asm/mem-layout.h +++ b/arch/frv/include/asm/mem-layout.h @@ -35,8 +35,8 @@ * the slab must be aligned such that load- and store-double instructions don't * fault if used */ -#define ARCH_KMALLOC_MINALIGN 8 -#define ARCH_SLAB_MINALIGN 8 +#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES +#define ARCH_SLAB_MINALIGN L1_CACHE_BYTES /*****************************************************************************/ /* |
