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author | Jean-François Têtu <jean-francois.tetu@savoirfairelinux.com> | 2017-09-22 17:44:28 -0400 |
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committer | Mark Brown <broonie@kernel.org> | 2017-09-25 12:05:06 -0700 |
commit | f53ee247ad546183fc13739adafc5579b9f0ebc0 (patch) | |
tree | 29af8d51859e8629c96e9320d16df442547499a5 /sound/soc/codecs/msm8916-wcd-digital.c | |
parent | 2bd6bf03f4c1c59381d62c61d03f6cc3fe71f66e (diff) | |
download | talos-op-linux-f53ee247ad546183fc13739adafc5579b9f0ebc0.tar.gz talos-op-linux-f53ee247ad546183fc13739adafc5579b9f0ebc0.zip |
ASoC: msm8916-wcd-digital: fix RX2 MIX1 and RX3 MIX1
The kcontrol for the third input (rxN_mix1_inp3) of both RX2
and RX3 mixers are not using the correct control register. This simple
patch fixes this.
Signed-off-by: Jean-François Têtu <jean-francois.tetu@savoirfairelinux.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/msm8916-wcd-digital.c')
-rw-r--r-- | sound/soc/codecs/msm8916-wcd-digital.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sound/soc/codecs/msm8916-wcd-digital.c b/sound/soc/codecs/msm8916-wcd-digital.c index 66df8f810f0d..a10a724eb448 100644 --- a/sound/soc/codecs/msm8916-wcd-digital.c +++ b/sound/soc/codecs/msm8916-wcd-digital.c @@ -238,7 +238,7 @@ static const struct soc_enum rx_mix2_inp1_chain_enum = SOC_ENUM_SINGLE( static const struct soc_enum rx2_mix1_inp_enum[] = { SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B1_CTL, 0, 6, rx_mix1_text), SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B1_CTL, 3, 6, rx_mix1_text), - SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B1_CTL, 0, 6, rx_mix1_text), + SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B2_CTL, 0, 6, rx_mix1_text), }; /* RX2 MIX2 */ @@ -249,7 +249,7 @@ static const struct soc_enum rx2_mix2_inp1_chain_enum = SOC_ENUM_SINGLE( static const struct soc_enum rx3_mix1_inp_enum[] = { SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B1_CTL, 0, 6, rx_mix1_text), SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B1_CTL, 3, 6, rx_mix1_text), - SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B1_CTL, 0, 6, rx_mix1_text), + SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B2_CTL, 0, 6, rx_mix1_text), }; /* DEC */ |