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| author | Shengjiu Wang <shengjiu.wang@freescale.com> | 2014-09-09 17:13:25 +0800 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@freescale.com> | 2014-09-16 10:09:39 +0800 |
| commit | dbaf381ffbf3acd4ac9a987f567a2b1a5edf6e62 (patch) | |
| tree | 7ef673b04004f91218d0532bc7768831a6769db2 /include/dt-bindings | |
| parent | dc4805c2e78ba5a22ea1632f3e3e4ee601a1743b (diff) | |
| download | talos-op-linux-dbaf381ffbf3acd4ac9a987f567a2b1a5edf6e62.tar.gz talos-op-linux-dbaf381ffbf3acd4ac9a987f567a2b1a5edf6e62.zip | |
ARM: clk-imx6sl: refine clock tree for SSI
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/imx6sl-clock.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h index f10a928fe2dd..9ce4e421096f 100644 --- a/include/dt-bindings/clock/imx6sl-clock.h +++ b/include/dt-bindings/clock/imx6sl-clock.h @@ -171,6 +171,9 @@ #define IMX6SL_PLL5_BYPASS 158 #define IMX6SL_PLL6_BYPASS 159 #define IMX6SL_PLL7_BYPASS 160 -#define IMX6SL_CLK_END 161 +#define IMX6SL_CLK_SSI1_IPG 161 +#define IMX6SL_CLK_SSI2_IPG 162 +#define IMX6SL_CLK_SSI3_IPG 163 +#define IMX6SL_CLK_END 164 #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ |
