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authorOlof Johansson <olof@lixom.net>2018-12-31 11:54:03 -0800
committerOlof Johansson <olof@lixom.net>2018-12-31 11:54:03 -0800
commitcac1fc8fb561ac766468394d49c3dd11a2b8cb44 (patch)
tree5483f72b13b766cfbd6f025d2a828fef3d1d0203 /drivers/pci/controller/dwc/pci-imx6.c
parentbd3fde386decf09317ff4a07cd0d05380a22f525 (diff)
parent54518ed45734bb7ebf2773b1d32120c62338cc93 (diff)
downloadtalos-op-linux-cac1fc8fb561ac766468394d49c3dd11a2b8cb44.tar.gz
talos-op-linux-cac1fc8fb561ac766468394d49c3dd11a2b8cb44.zip
Merge branch 'fixes' into next/soc
Merge in fixes here, since the last batch didn't make it in before the release of 4.20, and we might as well group them with this set of patches. * fixes: (822 commits) arm64: dts: renesas: draak: Fix CVBS input ARM: dts: Fix OMAP4430 SDP Ethernet startup ARM: dts: am335x-pdu001: Fix polarity of card detection input ARM: OMAP1: ams-delta: Fix audio permanently muted ARM: dts: omap5: Fix dual-role mode on Super-Speed port arm64: dts: rockchip: fix rk3399-rockpro64 regulator gpios ARM: dts: imx7d-nitrogen7: Fix the description of the Wifi clock ARM: imx: update the cpu power up timing setting on i.mx6sx Revert "arm64: dts: marvell: add CPU Idle power state support on Armada 7K/8K" ARM: dts: imx7d-pico: Describe the Wifi clock ARM: dts: realview: Fix some more duplicate regulator nodes MAINTAINERS: update entry for MMP platform ARM: mmp/mmp2: fix cpu_is_mmp2() on mmp2-dt MAINTAINERS: mediatek: Update SoC entry ARM: dts: bcm2837: Fix polarity of wifi reset GPIOs + Linux 4.20-rc5 Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'drivers/pci/controller/dwc/pci-imx6.c')
-rw-r--r--drivers/pci/controller/dwc/pci-imx6.c10
1 files changed, 1 insertions, 9 deletions
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 2cbef2d7c207..88af6bff945f 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -81,8 +81,6 @@ struct imx6_pcie {
#define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
-#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
-#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4)
#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
#define PCIE_PHY_CTRL_DATA_LOC 0
@@ -711,12 +709,6 @@ static int imx6_pcie_host_init(struct pcie_port *pp)
return 0;
}
-static int imx6_pcie_link_up(struct dw_pcie *pci)
-{
- return dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1) &
- PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
-}
-
static const struct dw_pcie_host_ops imx6_pcie_host_ops = {
.host_init = imx6_pcie_host_init,
};
@@ -749,7 +741,7 @@ static int imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
}
static const struct dw_pcie_ops dw_pcie_ops = {
- .link_up = imx6_pcie_link_up,
+ /* No special ops needed, but pcie-designware still expects this struct */
};
#ifdef CONFIG_PM_SLEEP
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