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authorMiquel Raynal <miquel.raynal@bootlin.com>2019-11-17 18:34:01 +0100
committerMiquel Raynal <miquel.raynal@bootlin.com>2019-11-17 18:34:01 +0100
commit8389a7b909f252e74ea92b2794de8d660cfee96e (patch)
treea947f3080e953e4a44417389b3f2b69d4817be2e /drivers/nvme/target/loop.c
parentad39b5a1ed68032292794b41a5f9e41ea69f8052 (diff)
parent83cba933a6db1dd4d7ac85170f99461fbc339eff (diff)
downloadtalos-op-linux-8389a7b909f252e74ea92b2794de8d660cfee96e.tar.gz
talos-op-linux-8389a7b909f252e74ea92b2794de8d660cfee96e.zip
Merge tag 'spi-nor/for-5.5' into mtd/next
SPI NOR core changes: - introduce 'struct spi_nor_controller_ops', - clean the Register Operations methods, - use dev_dbg insted of dev_err for low level info, - fix retlen handling in sst_write(), - fix silent truncations in spi_nor_read and spi_nor_read_raw(), - fix the clearing of QE bit on lock()/unlock(), - rework the disabling of the block write protection, - rework the Quad Enable methods, - make sure nor->spimem and nor->controller_ops are mutually exclusive, - set default Quad Enable method for ISSI flashes, - add support for few flashes. SPI NOR controller drivers changes: - intel-spi: - support chips without software sequencer, - add support for Intel Cannon Lake and Intel Comet Lake-H flashes.
Diffstat (limited to 'drivers/nvme/target/loop.c')
-rw-r--r--drivers/nvme/target/loop.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/nvme/target/loop.c b/drivers/nvme/target/loop.c
index 748a39fca771..11f5aea97d1b 100644
--- a/drivers/nvme/target/loop.c
+++ b/drivers/nvme/target/loop.c
@@ -157,8 +157,10 @@ static blk_status_t nvme_loop_queue_rq(struct blk_mq_hw_ctx *hctx,
iod->sg_table.sgl = iod->first_sgl;
if (sg_alloc_table_chained(&iod->sg_table,
blk_rq_nr_phys_segments(req),
- iod->sg_table.sgl, SG_CHUNK_SIZE))
+ iod->sg_table.sgl, SG_CHUNK_SIZE)) {
+ nvme_cleanup_cmd(req);
return BLK_STS_RESOURCE;
+ }
iod->req.sg = iod->sg_table.sgl;
iod->req.sg_cnt = blk_rq_map_sg(req->q, req, iod->sg_table.sgl);
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