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| author | ludovic.desroches@atmel.com <ludovic.desroches@atmel.com> | 2015-09-17 10:16:19 +0200 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2015-10-08 19:55:05 +0200 |
| commit | af951761d01c89eea8f1dcccf8010218e4b55817 (patch) | |
| tree | 41f5fa35918daed8aa7353fe7123bd83b224ada1 /drivers/mmc/host/sdhci.c | |
| parent | 2162d9f41e7c4778b96b8e3b97adcedbadc861f1 (diff) | |
| download | talos-op-linux-af951761d01c89eea8f1dcccf8010218e4b55817.tar.gz talos-op-linux-af951761d01c89eea8f1dcccf8010218e4b55817.zip | |
mmc: sdhci: add quirk SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST
The Atmel sdhci device needs a new quirk. sdhci_set_clock set the Clock
Control Register to 0 before computing the new value and writing it.
It disables the internal clock which causes a reset mecanism. If we
write the new value before this reset mecanism is done, it will prevent
the stabilisation of the internal clock, so a delay is needed. This
delay is about 2-3 cycles of the base clock. To be safe, a 1 ms delay is
used.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc/host/sdhci.c')
| -rw-r--r-- | drivers/mmc/host/sdhci.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 64b7fdbd1a9c..fbc7efdddcb5 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1160,6 +1160,8 @@ void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) host->mmc->actual_clock = 0; sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST) + mdelay(1); if (clock == 0) return; |
