diff options
author | Christophe Lombard <clombard@linux.vnet.ibm.com> | 2016-03-04 12:26:34 +0100 |
---|---|---|
committer | Michael Ellerman <mpe@ellerman.id.au> | 2016-03-09 13:05:52 +1100 |
commit | 444c4ba4616503baf68cffbf6748047d308b8cd2 (patch) | |
tree | c4290add66a6062c6b735d97b448c4260c137d3b /drivers/misc/cxl/cxl.h | |
parent | c0efa9aee8504ce16250320c1e5464bdb7e24400 (diff) | |
download | talos-op-linux-444c4ba4616503baf68cffbf6748047d308b8cd2.tar.gz talos-op-linux-444c4ba4616503baf68cffbf6748047d308b8cd2.zip |
cxl: New hcalls to support cxl adapters
The hypervisor calls provide an interface with a coherent platform
facility and function. It matches version 0.16 of the 'PAPR changes'
document.
The following hcalls are supported:
H_ATTACH_CA_PROCESS Attach a process element to a coherent platform
function.
H_DETACH_CA_PROCESS Detach a process element from a coherent
platform function.
H_CONTROL_CA_FUNCTION Allow the partition to manipulate or query
certain coherent platform function behaviors.
H_COLLECT_CA_INT_INFO Collect interrupt info about a coherent.
platform function after an interrupt occurred
H_CONTROL_CA_FAULTS Control the operation of a coherent platform
function after a fault occurs.
H_DOWNLOAD_CA_FACILITY Support for downloading a base adapter image to
the coherent platform facility, and for
validating the entire image after the download.
H_CONTROL_CA_FACILITY Allow the partition to manipulate or query
certain coherent platform facility behaviors.
Co-authored-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Manoj Kumar <manoj@linux.vnet.ibm.com>
Acked-by: Ian Munsie <imunsie@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'drivers/misc/cxl/cxl.h')
-rw-r--r-- | drivers/misc/cxl/cxl.h | 23 |
1 files changed, 21 insertions, 2 deletions
diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h index c7ed26549565..ac655a698e41 100644 --- a/drivers/misc/cxl/cxl.h +++ b/drivers/misc/cxl/cxl.h @@ -688,6 +688,7 @@ void cxl_prefault(struct cxl_context *ctx, u64 wed); struct cxl *get_cxl_adapter(int num); int cxl_alloc_sst(struct cxl_context *ctx); +void cxl_dump_debug_buffer(void *addr, size_t size); void init_cxl_native(void); @@ -701,16 +702,34 @@ unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq, void cxl_unmap_irq(unsigned int virq, void *cookie); int __detach_context(struct cxl_context *ctx); -/* This matches the layout of the H_COLLECT_CA_INT_INFO retbuf */ +/* + * This must match the layout of the H_COLLECT_CA_INT_INFO retbuf defined + * in PAPR. + * A word about endianness: a pointer to this structure is passed when + * calling the hcall. However, it is not a block of memory filled up by + * the hypervisor. The return values are found in registers, and copied + * one by one when returning from the hcall. See the end of the call to + * plpar_hcall9() in hvCall.S + * As a consequence: + * - we don't need to do any endianness conversion + * - the pid and tid are an exception. They are 32-bit values returned in + * the same 64-bit register. So we do need to worry about byte ordering. + */ struct cxl_irq_info { u64 dsisr; u64 dar; u64 dsr; +#ifndef CONFIG_CPU_LITTLE_ENDIAN u32 pid; u32 tid; +#else + u32 tid; + u32 pid; +#endif u64 afu_err; u64 errstat; - u64 padding[3]; /* to match the expected retbuf size for plpar_hcall9 */ + u64 proc_handle; + u64 padding[2]; /* to match the expected retbuf size for plpar_hcall9 */ }; void cxl_assign_psn_space(struct cxl_context *ctx); |