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author | Takashi Iwai <tiwai@suse.de> | 2018-10-22 23:26:37 +0200 |
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committer | Takashi Iwai <tiwai@suse.de> | 2018-10-22 23:26:37 +0200 |
commit | 5e3cdecf7834a764b9d24f6e696adf3e03813fab (patch) | |
tree | 2a1083ca53de6992b04d5026f6cb3310adccac04 /drivers/infiniband/hw/hfi1/pcie.c | |
parent | b5a229350b72b929edac5ba77c825f8ebb413533 (diff) | |
parent | 65dfb6d6dd2850f3f99f08536d2b14190350c854 (diff) | |
download | talos-op-linux-5e3cdecf7834a764b9d24f6e696adf3e03813fab.tar.gz talos-op-linux-5e3cdecf7834a764b9d24f6e696adf3e03813fab.zip |
Merge tag 'asoc-v5.0' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus
ASoC: Updates for v5.0/v4.20
As ever there's a lot of small and driver specific changes going on
here, but we do also have some relatively large changes in the core
thanks to the hard work of Charles and Morimoto-san:
- More component transitions from Morimoto-san, I think we're about
finished with this. Thanks for all the hard work!
- Morimoto-san also added a bunch of for_each_foo macros
- A bunch of cleanups and fixes for DAPM from Charles.
- MCLK support for several different devices, including CS42L51, STM32
SAI, and MAX98373.
- Support for Allwinner A64 CODEC analog, Intel boards with DA7219 and
MAX98927, Meson AXG PDM inputs, Nuvoton NAU8822, Renesas R8A7744 and
TI PCM3060.
Diffstat (limited to 'drivers/infiniband/hw/hfi1/pcie.c')
-rw-r--r-- | drivers/infiniband/hw/hfi1/pcie.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/drivers/infiniband/hw/hfi1/pcie.c b/drivers/infiniband/hw/hfi1/pcie.c index eec83757d55f..6c967dde58e7 100644 --- a/drivers/infiniband/hw/hfi1/pcie.c +++ b/drivers/infiniband/hw/hfi1/pcie.c @@ -893,14 +893,11 @@ static int trigger_sbr(struct hfi1_devdata *dd) } /* - * A secondary bus reset (SBR) issues a hot reset to our device. - * The following routine does a 1s wait after the reset is dropped - * per PCI Trhfa (recovery time). PCIe 3.0 section 6.6.1 - - * Conventional Reset, paragraph 3, line 35 also says that a 1s - * delay after a reset is required. Per spec requirements, - * the link is either working or not after that point. + * This is an end around to do an SBR during probe time. A new API needs + * to be implemented to have cleaner interface but this fixes the + * current brokenness */ - return pci_reset_bus(dev); + return pci_bridge_secondary_bus_reset(dev->bus->self); } /* |