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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2016-04-28 09:56:43 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2016-04-28 12:17:32 +0100 |
| commit | ff55b5e89289bc4e726848ee75db6aafce3093a7 (patch) | |
| tree | c243b3d791a7a9c03b73b14cbeb32547e4430c69 /drivers/gpu/drm | |
| parent | b0ebde395d35dd1c592817c0f5381842f161b81a (diff) | |
| download | talos-op-linux-ff55b5e89289bc4e726848ee75db6aafce3093a7.tar.gz talos-op-linux-ff55b5e89289bc4e726848ee75db6aafce3093a7.zip | |
drm/i915: Consolidate L3 remapping LRI
We can use a single MI_LOAD_REGISTER_IMM command packet to write all the
L3 remapping registers, shrinking the number of bytes required to emit
the context switch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1461833819-3991-9-git-send-email-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_context.c | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index ec0122bc4263..3a09cc8039db 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -603,16 +603,14 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) { + u32 *remap_info = req->i915->l3_parity.remap_info[slice]; struct intel_engine_cs *engine = req->engine; - struct drm_device *dev = engine->dev; - struct drm_i915_private *dev_priv = dev->dev_private; - u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; int i, ret; - if (!HAS_L3_DPF(dev) || !remap_info) + if (!remap_info) return 0; - ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3); + ret = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2); if (ret) return ret; @@ -621,15 +619,15 @@ int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) * here because no other code should access these registers other than * at initialization time. */ - for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) { - intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); + intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4)); + for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i)); intel_ring_emit(engine, remap_info[i]); } - + intel_ring_emit(engine, MI_NOOP); intel_ring_advance(engine); - return ret; + return 0; } static inline bool skip_rcs_switch(struct intel_engine_cs *engine, |
