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authorAlex Deucher <alexander.deucher@amd.com>2013-04-12 13:52:52 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-06-27 10:49:18 -0400
commit2948f5e6c211eccd58b81c15a410d9f3d9cda657 (patch)
tree86324d51dc6edbd9f279a4c955d6444aed23c1c1 /drivers/gpu/drm/radeon/r600d.h
parent138e4e16f0e1d7dee8e6d0534147e15c0a3d94d5 (diff)
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drm/radeon: properly set up the RLC on ON/LN/TN (v3)
This is required for certain advanced functionality. v2: save/restore list takes dword offsets v3: rebase on gpu reset changes Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600d.h')
-rw-r--r--drivers/gpu/drm/radeon/r600d.h4
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 79df558f8c40..a3f926c8f5e9 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -684,10 +684,6 @@
#define RLC_UCODE_ADDR 0x3f2c
#define RLC_UCODE_DATA 0x3f30
-/* new for TN */
-#define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10
-#define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20
-
#define SRBM_SOFT_RESET 0xe60
# define SOFT_RESET_DMA (1 << 12)
# define SOFT_RESET_RLC (1 << 13)
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