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authorJon Hunter <jonathanh@nvidia.com>2016-07-01 14:21:38 +0100
committerThierry Reding <treding@nvidia.com>2016-07-14 14:57:03 +0200
commitf8c79120aa1d9eedb36cdadbd23489056a9f7b90 (patch)
tree138c97ec178bb10bf78bd543b557d8e29ea89e83 /drivers/gpu/drm/radeon/r600_blit_shaders.h
parent64230aa075864f7c8e270b583bca685304246b57 (diff)
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drm/tegra: sor: Prepare for generic PM domain support
The SOR driver for Tegra requires the SOR power partition to be enabled. Now that Tegra supports the generic PM domain framework we manage the SOR power partition via this framework. However, the sequence for gating/ungating the SOR power partition requires that the SOR reset is asserted/de-asserted at the time the SOR power partition is gated/ungated, respectively. Now that the reset control core assumes that resets are exclusive, the Tegra generic PM domain code and the SOR driver cannot request the same reset unless we mark the reset as shared. Sharing resets will not work in this case because we cannot guarantee that the reset will be asserted/de-asserted at the appropriate time. Therefore, given that the Tegra generic PM domain code will handle the resets, do not request the reset in the SOR driver if the SOR device has a PM domain associated. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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