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| author | Hai Li <hali@codeaurora.org> | 2015-09-11 15:56:09 -0400 |
|---|---|---|
| committer | Rob Clark <robdclark@gmail.com> | 2015-10-22 15:39:54 -0400 |
| commit | e01b1bfd88f9c5ec32b471a5a696a79f45740e63 (patch) | |
| tree | 0d86b5bf966f9e6d3a5ea9ea614c3bc6e6b7abec /drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | |
| parent | 556a76e51b5c8e16986e2cc0a5e14306a4e2505a (diff) | |
| download | talos-op-linux-e01b1bfd88f9c5ec32b471a5a696a79f45740e63.tar.gz talos-op-linux-e01b1bfd88f9c5ec32b471a5a696a79f45740e63.zip | |
drm/msm/dsi: Updata LNn_CFG4 register settings for 28nm PHY
The current settings for 28nm PHY data lane CFG4 registers do
not work with certain panels. This change is to modify them to
hw recommended values.
Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c')
0 files changed, 0 insertions, 0 deletions
