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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2014-11-21 21:54:27 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-12-03 09:29:37 +0100 |
| commit | 59ea90543f57a40827d7d1e528d657b8cc7161b1 (patch) | |
| tree | 18aa9d9bc5e850d3e3d86fa15727a2a94e105672 /drivers/gpu/drm/i915/intel_uncore.c | |
| parent | ca83b9361bf70d5d4171ba54a598a8c8f981f091 (diff) | |
| download | talos-op-linux-59ea90543f57a40827d7d1e528d657b8cc7161b1.tar.gz talos-op-linux-59ea90543f57a40827d7d1e528d657b8cc7161b1.zip | |
drm/i915: Implement GPU reset for 915/945
915/945 have the same reset registers as 965, so share the code.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_uncore.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_uncore.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index c333d9c37f11..68dc32058587 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1345,27 +1345,27 @@ int i915_get_reset_stats_ioctl(struct drm_device *dev, return 0; } -static int i965_reset_complete(struct drm_device *dev) +static int i915_reset_complete(struct drm_device *dev) { u8 gdrst; - pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); + pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst); return (gdrst & GRDOM_RESET_STATUS) == 0; } -static int i965_do_reset(struct drm_device *dev) +static int i915_do_reset(struct drm_device *dev) { /* assert reset for at least 20 usec */ - pci_write_config_byte(dev->pdev, I965_GDRST, GRDOM_RESET_ENABLE); + pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE); udelay(20); - pci_write_config_byte(dev->pdev, I965_GDRST, 0); + pci_write_config_byte(dev->pdev, I915_GDRST, 0); - return wait_for(i965_reset_complete(dev), 500); + return wait_for(i915_reset_complete(dev), 500); } static int g4x_reset_complete(struct drm_device *dev) { u8 gdrst; - pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); + pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst); return (gdrst & GRDOM_RESET_ENABLE) == 0; } @@ -1374,7 +1374,7 @@ static int g4x_do_reset(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; int ret; - pci_write_config_byte(dev->pdev, I965_GDRST, + pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RENDER | GRDOM_RESET_ENABLE); ret = wait_for(g4x_reset_complete(dev), 500); if (ret) @@ -1384,7 +1384,7 @@ static int g4x_do_reset(struct drm_device *dev) I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); POSTING_READ(VDECCLK_GATE_D); - pci_write_config_byte(dev->pdev, I965_GDRST, + pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_MEDIA | GRDOM_RESET_ENABLE); ret = wait_for(g4x_reset_complete(dev), 500); if (ret) @@ -1394,7 +1394,7 @@ static int g4x_do_reset(struct drm_device *dev) I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); POSTING_READ(VDECCLK_GATE_D); - pci_write_config_byte(dev->pdev, I965_GDRST, 0); + pci_write_config_byte(dev->pdev, I915_GDRST, 0); return 0; } @@ -1452,8 +1452,8 @@ int intel_gpu_reset(struct drm_device *dev) return ironlake_do_reset(dev); else if (IS_G4X(dev)) return g4x_do_reset(dev); - else if (IS_GEN4(dev)) - return i965_do_reset(dev); + else if (IS_GEN4(dev) || (IS_GEN3(dev) && !IS_G33(dev))) + return i915_do_reset(dev); else return -ENODEV; } |
