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| author | Imre Deak <imre.deak@intel.com> | 2016-04-20 20:27:57 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2016-04-22 15:12:05 +0300 |
| commit | f62c79b33ff150da40fcdfc8cd48d0dd77f62902 (patch) | |
| tree | 5d9941fe3511347de01a645e74a3efcbe636250b /drivers/gpu/drm/i915/intel_runtime_pm.c | |
| parent | da2f41d107e57074814ad44f4cea2b7befe3b7c4 (diff) | |
| download | talos-op-linux-f62c79b33ff150da40fcdfc8cd48d0dd77f62902.tar.gz talos-op-linux-f62c79b33ff150da40fcdfc8cd48d0dd77f62902.zip | |
drm/i915/bxt: Enable DC5 during runtime resume
Right after runtime resume we know that we can re-enable DC5, since we
just disabled DC9 and power well 2 is disabled. So enable DC5 explicitly
instead of delaying this until the next time we disable power well 2.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1461173277-16090-5-git-send-email-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_runtime_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_runtime_pm.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 8fff0800b4ed..7fb1da4e7fc3 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -582,7 +582,7 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) assert_csr_loaded(dev_priv); } -static void gen9_enable_dc5(struct drm_i915_private *dev_priv) +void gen9_enable_dc5(struct drm_i915_private *dev_priv) { assert_can_enable_dc5(dev_priv); |
