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authorChris Wilson <chris@chris-wilson.co.uk>2018-06-11 18:18:24 +0100
committerChris Wilson <chris@chris-wilson.co.uk>2018-06-12 09:09:38 +0100
commit68a8570375df647cf8b6626d63917b564dd9390e (patch)
tree33e39d284e7fe83c6285d29893a610a888e2833c /drivers/gpu/drm/i915/intel_ringbuffer.c
parent467d35789e5a4f47428b65ef711b30fdabbb0fd4 (diff)
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drm/i915/gtt: Invalidate GGTT caches after writing the gen6 page directories
When we update the gen6 ppgtt page directories, we do so by writing the new address into a reserved slot in the GGTT. It appears that when the GPU reads that entry from the gsm, it uses its small cache and that we need to invalidate that cache after writing. We don't see an issue currently as we prefill the ppgtt page directories on creation; and only create the single aliasing_ppgtt long before we start using the GGTT (and so before the cache may have a conflicting entry). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Matthew Auld <matthew.william.auld@gmail.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180611171825.13678-1-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
0 files changed, 0 insertions, 0 deletions
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