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| author | Patrik Jakobsson <patrik.r.jakobsson@gmail.com> | 2013-02-13 22:20:22 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-02-20 00:21:46 +0100 |
| commit | 4f7dfb6788dd022446847fbbfbe45e13bedb5be2 (patch) | |
| tree | 822ff1448493a7bf474805dc210ed74b50ddb7d3 /drivers/gpu/drm/i915/intel_display.c | |
| parent | 53a7d2d15ef45fb892defaf624ad6db7d528d8ac (diff) | |
| download | talos-op-linux-4f7dfb6788dd022446847fbbfbe45e13bedb5be2.tar.gz talos-op-linux-4f7dfb6788dd022446847fbbfbe45e13bedb5be2.zip | |
drm/i915: Set i9xx sdvo clock limits according to specifications
The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9.
Since we do all calculations based on them being register values (which are
subtracted by 2) we need to specify them accordingly.
Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56359
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index aa31b96e5301..3e6dadf902de 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -154,8 +154,8 @@ static const intel_limit_t intel_limits_i9xx_sdvo = { .vco = { .min = 1400000, .max = 2800000 }, .n = { .min = 1, .max = 6 }, .m = { .min = 70, .max = 120 }, - .m1 = { .min = 10, .max = 22 }, - .m2 = { .min = 5, .max = 9 }, + .m1 = { .min = 8, .max = 18 }, + .m2 = { .min = 3, .max = 7 }, .p = { .min = 5, .max = 80 }, .p1 = { .min = 1, .max = 8 }, .p2 = { .dot_limit = 200000, |
