diff options
| author | Rodrigo Vivi <vivijim@rdvivi-cozumel.jf.intel.com> | 2019-01-24 14:50:02 -0800 |
|---|---|---|
| committer | Rodrigo Vivi <vivijim@rdvivi-cozumel.jf.intel.com> | 2019-01-24 14:50:04 -0800 |
| commit | ff00d85b4df97bf9cc7082b3d0dc2c317b946aa2 (patch) | |
| tree | 7dae9d0338e0d894dd0cb80c16fff18d28918f58 /drivers/gpu/drm/i915/gvt/fb_decoder.c | |
| parent | 0cdc1d07b4616f164978e8f1b3a5fe8b0a3ac835 (diff) | |
| parent | 2e679d48f38c378650db403b4ba2248adf0691b2 (diff) | |
| download | talos-op-linux-ff00d85b4df97bf9cc7082b3d0dc2c317b946aa2.tar.gz talos-op-linux-ff00d85b4df97bf9cc7082b3d0dc2c317b946aa2.zip | |
Merge tag 'gvt-next-2019-01-24' of https://github.com/intel/gvt-linux into drm-intel-next-queued
gvt-next-2019-01-24
- split kvmgt as seperate module (Zhenyu)
- Coffeelake GVT support (Fred)
- const treatment and change for kernel type (Jani)
Signed-off-by: Rodrigo Vivi <vivijim@rdvivi-cozumel.jf.intel.com>
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190124054048.GO7203@zhen-hp.sh.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/fb_decoder.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/fb_decoder.c | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index 85e6736f0a32..65e847392aea 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -151,9 +151,7 @@ static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe, u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask; u32 stride = stride_reg; - if (IS_SKYLAKE(dev_priv) - || IS_KABYLAKE(dev_priv) - || IS_BROXTON(dev_priv)) { + if (INTEL_GEN(dev_priv) >= 9) { switch (tiled) { case PLANE_CTL_TILED_LINEAR: stride = stride_reg * 64; @@ -217,9 +215,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, if (!plane->enabled) return -ENODEV; - if (IS_SKYLAKE(dev_priv) - || IS_KABYLAKE(dev_priv) - || IS_BROXTON(dev_priv)) { + if (INTEL_GEN(dev_priv) >= 9) { plane->tiled = val & PLANE_CTL_TILED_MASK; fmt = skl_format_to_drm( val & PLANE_CTL_FORMAT_MASK, @@ -260,9 +256,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, } plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled, - (IS_SKYLAKE(dev_priv) - || IS_KABYLAKE(dev_priv) - || IS_BROXTON(dev_priv)) ? + (INTEL_GEN(dev_priv) >= 9) ? (_PRI_PLANE_STRIDE_MASK >> 6) : _PRI_PLANE_STRIDE_MASK, plane->bpp); |
