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authorPatrik Jakobsson <patrik.r.jakobsson@gmail.com>2013-08-14 19:14:17 +0200
committerPatrik Jakobsson <patrik.r.jakobsson@gmail.com>2013-08-14 20:44:52 +0200
commit28a8194c12f8c8bb46aecd4cb1f36bac716714c4 (patch)
treeecefead41789d5dd66d9970c5d45462cf17439f4 /drivers/gpu/drm/gma500
parent367e44080e20f77fa7b0f2db83fd6367da59b6c3 (diff)
downloadtalos-op-linux-28a8194c12f8c8bb46aecd4cb1f36bac716714c4.tar.gz
talos-op-linux-28a8194c12f8c8bb46aecd4cb1f36bac716714c4.zip
drm/gma500/cdv: Add and hook up chip op for watermarks
Add a callback hook to the chip ops struct to allow chips to have their specific fifo watermark update function. Currently only cdv actually tries to set wms based on crtc configuration but if/when the other chips needs it we can attach a callback for them as well. Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/gma500')
-rw-r--r--drivers/gpu/drm/gma500/cdv_device.c1
-rw-r--r--drivers/gpu/drm/gma500/cdv_device.h1
-rw-r--r--drivers/gpu/drm/gma500/cdv_intel_display.c2
-rw-r--r--drivers/gpu/drm/gma500/gma_display.c2
-rw-r--r--drivers/gpu/drm/gma500/gma_display.h2
-rw-r--r--drivers/gpu/drm/gma500/psb_drv.h1
6 files changed, 5 insertions, 4 deletions
diff --git a/drivers/gpu/drm/gma500/cdv_device.c b/drivers/gpu/drm/gma500/cdv_device.c
index daa45b5b3a45..747d903fe49f 100644
--- a/drivers/gpu/drm/gma500/cdv_device.c
+++ b/drivers/gpu/drm/gma500/cdv_device.c
@@ -656,4 +656,5 @@ const struct psb_ops cdv_chip_ops = {
.restore_regs = cdv_restore_display_registers,
.power_down = cdv_power_down,
.power_up = cdv_power_up,
+ .update_wm = cdv_update_wm,
};
diff --git a/drivers/gpu/drm/gma500/cdv_device.h b/drivers/gpu/drm/gma500/cdv_device.h
index 602406bb6d0f..9e4805627450 100644
--- a/drivers/gpu/drm/gma500/cdv_device.h
+++ b/drivers/gpu/drm/gma500/cdv_device.h
@@ -26,3 +26,4 @@ extern void cdv_hdmi_init(struct drm_device *dev, struct psb_intel_mode_device *
int reg);
extern struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
struct drm_crtc *crtc);
+extern void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc);
diff --git a/drivers/gpu/drm/gma500/cdv_intel_display.c b/drivers/gpu/drm/gma500/cdv_intel_display.c
index ee8a502348ce..feacbbaabf14 100644
--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
@@ -532,7 +532,7 @@ void cdv_intel_disable_self_refresh(struct drm_device *dev)
}
-void cdv_intel_update_watermark(struct drm_device *dev, struct drm_crtc *crtc)
+void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc)
{
if (cdv_intel_single_pipe_active(dev)) {
diff --git a/drivers/gpu/drm/gma500/gma_display.c b/drivers/gpu/drm/gma500/gma_display.c
index cd253caf5672..fe972c930c2c 100644
--- a/drivers/gpu/drm/gma500/gma_display.c
+++ b/drivers/gpu/drm/gma500/gma_display.c
@@ -321,7 +321,7 @@ void gma_crtc_dpms(struct drm_crtc *crtc, int mode)
}
if (IS_CDV(dev))
- cdv_intel_update_watermark(dev, crtc);
+ dev_priv->ops->update_wm(dev, crtc);
/* Set FIFO watermarks */
REG_WRITE(DSPARB, 0x3F3E);
diff --git a/drivers/gpu/drm/gma500/gma_display.h b/drivers/gpu/drm/gma500/gma_display.h
index 1044c165c714..9a4e8941bd25 100644
--- a/drivers/gpu/drm/gma500/gma_display.h
+++ b/drivers/gpu/drm/gma500/gma_display.h
@@ -103,6 +103,4 @@ extern bool gma_find_best_pll(const struct gma_limit_t *limit,
/* Cedarview specific functions */
extern void cdv_intel_disable_self_refresh(struct drm_device *dev);
-extern void cdv_intel_update_watermark(struct drm_device *dev,
- struct drm_crtc *crtc);
#endif
diff --git a/drivers/gpu/drm/gma500/psb_drv.h b/drivers/gpu/drm/gma500/psb_drv.h
index ed1e567b7e3b..effd69502be5 100644
--- a/drivers/gpu/drm/gma500/psb_drv.h
+++ b/drivers/gpu/drm/gma500/psb_drv.h
@@ -695,6 +695,7 @@ struct psb_ops {
int (*restore_regs)(struct drm_device *dev);
int (*power_up)(struct drm_device *dev);
int (*power_down)(struct drm_device *dev);
+ void (*update_wm)(struct drm_device *dev, struct drm_crtc *crtc);
void (*lvds_bl_power)(struct drm_device *dev, bool on);
#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
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