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| author | Shirish S <shirish.s@amd.com> | 2018-11-16 06:50:28 +0000 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-11-26 15:46:52 -0500 |
| commit | 00fedbe629bfc0a51c07b6e665265ce31d8b6f3c (patch) | |
| tree | 6dbe99c2dc9235c06f0011dbab18575a738588aa /drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c | |
| parent | b333730d126efcc8f2fad60df3c9b3971ff59833 (diff) | |
| download | talos-op-linux-00fedbe629bfc0a51c07b6e665265ce31d8b6f3c.tar.gz talos-op-linux-00fedbe629bfc0a51c07b6e665265ce31d8b6f3c.zip | |
Revert "drm/amd/powerplay: Enable/Disable NBPSTATE on On/OFF of UVD"
This reverts commit dbd8299c32f6f413f6cfe322fe0308f3cfc577e8.
Reason for revert:
This patch sends msg PPSMC_MSG_DisableLowMemoryPstate(0x002e)
in wrong of sequence to SMU which is before PPSMC_MSG_UVDPowerON (0x0008).
This leads to SMU failing to service the request as it is
dependent on UVD to be powered ON, since it accesses UVD
registers.
This msg should ideally be sent only when the UVD is about to decode
a 4k video.
Signed-off-by: Shirish S <shirish.s@amd.com>
Signed-off-by: suresh guttula <suresh.guttula@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c index fef111ddb736..53cf787560f7 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c @@ -1228,17 +1228,14 @@ static int smu8_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, static int smu8_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr) { - if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) { - smu8_nbdpm_pstate_enable_disable(hwmgr, true, true); + if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF); - } return 0; } static int smu8_dpm_powerup_uvd(struct pp_hwmgr *hwmgr) { if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) { - smu8_nbdpm_pstate_enable_disable(hwmgr, false, true); return smum_send_msg_to_smc_with_parameter( hwmgr, PPSMC_MSG_UVDPowerON, |
