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| author | Alex Deucher <alexander.deucher@amd.com> | 2019-02-15 14:40:26 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-10-15 15:55:31 -0400 |
| commit | 8763eb7ae9ff06793f10135a93651c79272a6099 (patch) | |
| tree | b144d59ef3944f9d275db6da195d57835d11bdc4 /drivers/gpu/drm/amd/include | |
| parent | 5337aae9b5dbf1a166b27ddc874f724a77a36fe8 (diff) | |
| download | talos-op-linux-8763eb7ae9ff06793f10135a93651c79272a6099.tar.gz talos-op-linux-8763eb7ae9ff06793f10135a93651c79272a6099.zip | |
drm/amdgpu: add new BIF 4.1 register for BACO
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h index a761ba07f937..fce965984e76 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h +++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h @@ -27,6 +27,7 @@ #define mmMM_INDEX 0x0 #define mmMM_INDEX_HI 0x6 #define mmMM_DATA 0x1 +#define mmCC_BIF_BX_FUSESTRAP0 0x14D7 #define mmBUS_CNTL 0x1508 #define mmCONFIG_CNTL 0x1509 #define mmCONFIG_MEMSIZE 0x150a diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h index 8fbfd0261d27..39cc4880beb4 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h @@ -32,6 +32,8 @@ #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 #define MM_DATA__MM_DATA_MASK 0xffffffff #define MM_DATA__MM_DATA__SHIFT 0x0 +#define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2 +#define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1 #define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1 #define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x0 #define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2 |
