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| author | Mikita Lipski <mikita.lipski@amd.com> | 2017-10-17 15:29:22 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-12-06 12:47:22 -0500 |
| commit | fa2123dbccdc881fae02aaf8b05758db53d62955 (patch) | |
| tree | cdbeaec656d934980a48b8e60a97409ea587328c /drivers/gpu/drm/amd/display/dc/inc | |
| parent | 79c631239a83aeb3e13216f2eda1741650645d64 (diff) | |
| download | talos-op-linux-fa2123dbccdc881fae02aaf8b05758db53d62955.tar.gz talos-op-linux-fa2123dbccdc881fae02aaf8b05758db53d62955.zip | |
drm/amd/display: Multi display synchronization logic
This feature synchronizes multiple displays with various timings
to a display with the highest refresh rate
it is enabled if edid caps flag multi_display_sync is set to one
There are limitations on refresh rates allowed
that can be synchronized. That would
prevent from underflow and other potential
corruptions.
Multi display synchronization is using the
same functions as timing_sync in order to minimize
redunduncy and decision to disable synchronization is
based on trigger parametre set in DM
Feature is developed for DCN1 and DCE11
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 5 |
2 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index c6ab38c5b2be..75f7a01b9175 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -158,7 +158,11 @@ struct timing_generator_funcs { const struct dcp_gsl_params *gsl_params); void (*unlock)(struct timing_generator *tg); void (*lock)(struct timing_generator *tg); - void (*enable_reset_trigger)(struct timing_generator *tg, int source_tg_inst); + void (*enable_reset_trigger)(struct timing_generator *tg, + int source_tg_inst); + void (*enable_crtc_reset)(struct timing_generator *tg, + int source_tg_inst, + struct crtc_trigger_info *crtc_tp); void (*disable_reset_trigger)(struct timing_generator *tg); void (*tear_down_global_swap_lock)(struct timing_generator *tg); void (*enable_advanced_request)(struct timing_generator *tg, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 8734689a9245..cebbba345889 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -114,6 +114,11 @@ struct hw_sequencer_funcs { int group_size, struct pipe_ctx *grouped_pipes[]); + void (*enable_per_frame_crtc_position_reset)( + struct dc *dc, + int group_size, + struct pipe_ctx *grouped_pipes[]); + void (*enable_display_pipe_clock_gating)( struct dc_context *ctx, bool clock_gating); |
