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authorThomas Gleixner <tglx@linutronix.de>2018-02-16 15:47:26 +0100
committerThomas Gleixner <tglx@linutronix.de>2018-02-16 15:47:26 +0100
commit6dee6ae9d62642e81def4d461d71f13a6496ab59 (patch)
tree6c75d416c427a59f190e197ad83fe59b7bebf656 /drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
parent1beaeacdc88b537703d04d5536235d0bbb36db93 (diff)
parent0b24a0bbe2147815d982d9335c41bb10c04f40bc (diff)
downloadtalos-op-linux-6dee6ae9d62642e81def4d461d71f13a6496ab59.tar.gz
talos-op-linux-6dee6ae9d62642e81def4d461d71f13a6496ab59.zip
Merge tag 'irqchip-4.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent
Pull irqchip updates for 4.16-rc2 from Marc Zyngier - A MIPS GIC fix for spurious, masked interrupts - A fix for a subtle IPI bug in GICv3 - Do not probe GICv3 ITSs that are marked as disabled - Multi-MSI support for GICv2m - Various cleanups
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h30
1 files changed, 24 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 8734689a9245..4c0aa56f7bae 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -28,6 +28,7 @@
#include "dc_types.h"
#include "clock_source.h"
#include "inc/hw/timing_generator.h"
+#include "inc/hw/opp.h"
#include "inc/hw/link_encoder.h"
#include "core_status.h"
@@ -39,6 +40,12 @@ enum pipe_gating_control {
struct dce_hwseq_wa {
bool blnd_crtc_trigger;
+ bool DEGVIDCN10_253;
+ bool false_optc_underflow;
+};
+
+struct hwseq_wa_state {
+ bool DEGVIDCN10_253_applied;
};
struct dce_hwseq {
@@ -47,6 +54,7 @@ struct dce_hwseq {
const struct dce_hwseq_shift *shifts;
const struct dce_hwseq_mask *masks;
struct dce_hwseq_wa wa;
+ struct hwseq_wa_state wa_state;
};
struct pipe_ctx;
@@ -114,6 +122,11 @@ struct hw_sequencer_funcs {
int group_size,
struct pipe_ctx *grouped_pipes[]);
+ void (*enable_per_frame_crtc_position_reset)(
+ struct dc *dc,
+ int group_size,
+ struct pipe_ctx *grouped_pipes[]);
+
void (*enable_display_pipe_clock_gating)(
struct dc_context *ctx,
bool clock_gating);
@@ -124,11 +137,7 @@ struct hw_sequencer_funcs {
struct dc_bios *dcb,
enum pipe_gating_control power_gating);
- void (*power_down_front_end)(struct dc *dc, int fe_idx);
-
- void (*power_on_front_end)(struct dc *dc,
- struct pipe_ctx *pipe,
- struct dc_state *context);
+ void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);
void (*update_info_frame)(struct pipe_ctx *pipe_ctx);
@@ -178,12 +187,17 @@ struct hw_sequencer_funcs {
void (*ready_shared_resources)(struct dc *dc, struct dc_state *context);
void (*optimize_shared_resources)(struct dc *dc);
+ void (*pplib_apply_display_requirements)(
+ struct dc *dc,
+ struct dc_state *context);
void (*edp_power_control)(
- struct link_encoder *enc,
+ struct dc_link *link,
bool enable);
void (*edp_backlight_control)(
struct dc_link *link,
bool enable);
+ void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
+
};
void color_space_to_black_color(
@@ -194,4 +208,8 @@ void color_space_to_black_color(
bool hwss_wait_for_blank_complete(
struct timing_generator *tg);
+const uint16_t *find_color_matrix(
+ enum dc_color_space color_space,
+ uint32_t *array_size);
+
#endif /* __DC_HW_SEQUENCER_H__ */
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