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| author | abdoulaye berthe <abdoulaye.berthe@amd.com> | 2019-08-13 09:24:10 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-10-17 16:24:34 -0400 |
| commit | 8276dd871fd4240037cffb3904eda2dfe028fd85 (patch) | |
| tree | 9431076a246b832d037aa4bf8bb06de6aa893a7d /drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | |
| parent | 64c5cc93677c115fdb4c3860a54466c836a1591b (diff) | |
| download | talos-op-linux-8276dd871fd4240037cffb3904eda2dfe028fd85.tar.gz talos-op-linux-8276dd871fd4240037cffb3904eda2dfe028fd85.zip | |
drm/amd/display: update register field access mechanism
1-add timeout length and multiplier fields to aux_control1 register
2-update access mechanism from macro constructed name to uint32_t
defined addresses.
3-define registers and field per asic family
Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index 7c52f7f9196c..fe7649b473a5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -293,6 +293,14 @@ static const struct dce_stream_encoder_mask se_mask = { SE_COMMON_MASK_SH_LIST_DCE120(_MASK) }; +static const struct dce110_aux_registers_shift aux_shift = { + DCE12_AUX_MASK_SH_LIST(__SHIFT) +}; + +static const struct dce110_aux_registers_mask aux_mask = { + DCE12_AUX_MASK_SH_LIST(_MASK) +}; + #define opp_regs(id)\ [id] = {\ OPP_DCE_120_REG_LIST(id),\ @@ -404,7 +412,9 @@ struct dce_aux *dce120_aux_engine_create( dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, - &aux_engine_regs[inst]); + &aux_engine_regs[inst], + &aux_mask, + &aux_shift); return &aux_engine->base; } |
