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| author | Thomas Gleixner <tglx@linutronix.de> | 2018-02-16 15:47:26 +0100 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2018-02-16 15:47:26 +0100 |
| commit | 6dee6ae9d62642e81def4d461d71f13a6496ab59 (patch) | |
| tree | 6c75d416c427a59f190e197ad83fe59b7bebf656 /drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | |
| parent | 1beaeacdc88b537703d04d5536235d0bbb36db93 (diff) | |
| parent | 0b24a0bbe2147815d982d9335c41bb10c04f40bc (diff) | |
| download | talos-op-linux-6dee6ae9d62642e81def4d461d71f13a6496ab59.tar.gz talos-op-linux-6dee6ae9d62642e81def4d461d71f13a6496ab59.zip | |
Merge tag 'irqchip-4.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent
Pull irqchip updates for 4.16-rc2 from Marc Zyngier
- A MIPS GIC fix for spurious, masked interrupts
- A fix for a subtle IPI bug in GICv3
- Do not probe GICv3 ITSs that are marked as disabled
- Multi-MSI support for GICv2m
- Various cleanups
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/psp_v10_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c index 4e20d91d5d50..5a9fe24697f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c @@ -30,10 +30,9 @@ #include "soc15_common.h" #include "psp_v10_0.h" -#include "vega10/soc15ip.h" -#include "raven1/MP/mp_10_0_offset.h" -#include "raven1/GC/gc_9_1_offset.h" -#include "raven1/SDMA0/sdma0_4_1_offset.h" +#include "mp/mp_10_0_offset.h" +#include "gc/gc_9_1_offset.h" +#include "sdma0/sdma0_4_1_offset.h" MODULE_FIRMWARE("amdgpu/raven_asd.bin"); @@ -298,9 +297,10 @@ int psp_v10_0_cmd_submit(struct psp_context *psp, } static int -psp_v10_0_sram_map(unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, - unsigned int *sram_data_reg_offset, - enum AMDGPU_UCODE_ID ucode_id) +psp_v10_0_sram_map(struct amdgpu_device *adev, + unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, + unsigned int *sram_data_reg_offset, + enum AMDGPU_UCODE_ID ucode_id) { int ret = 0; @@ -395,7 +395,7 @@ bool psp_v10_0_compare_sram_data(struct psp_context *psp, uint32_t *ucode_mem = NULL; struct amdgpu_device *adev = psp->adev; - err = psp_v10_0_sram_map(&fw_sram_reg_val, &fw_sram_addr_reg_offset, + err = psp_v10_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, &fw_sram_data_reg_offset, ucode_type); if (err) return false; |
