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authorJiange Zhao <Jiange.Zhao@amd.com>2019-09-11 17:29:07 +0800
committerAlex Deucher <alexander.deucher@amd.com>2019-09-16 10:15:20 -0500
commitb05b69036f7499d7f3cb52554f3e3dad9fefe00c (patch)
treeaaa350b73bcc911a686ac54d6f07887db161c8ad /drivers/gpu/drm/amd/amdgpu/nv.c
parent51c0f58e9f6af3a387d14608033e6796a7ad90ee (diff)
downloadtalos-op-linux-b05b69036f7499d7f3cb52554f3e3dad9fefe00c.tar.gz
talos-op-linux-b05b69036f7499d7f3cb52554f3e3dad9fefe00c.zip
drm/amdgpu: For Navi12 SRIOV VF, register mailbox functions
Mailbox functions and interrupts are only for Navi12 VF. Register functions and irqs during initialization. Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/nv.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/nv.c19
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 285f1a1f1db5..44f539a7f411 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -54,6 +54,7 @@
#include "vcn_v2_0.h"
#include "dce_virtual.h"
#include "mes_v10_1.h"
+#include "mxgpu_nv.h"
static const struct amd_ip_funcs nv_common_ip_funcs;
@@ -427,6 +428,9 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
adev->nbio.funcs->detect_hw_virt(adev);
+ if (amdgpu_sriov_vf(adev))
+ adev->virt.ops = &xgpu_nv_virt_ops;
+
switch (adev->asic_type) {
case CHIP_NAVI10:
case CHIP_NAVI14:
@@ -667,16 +671,31 @@ static int nv_common_early_init(void *handle)
return -EINVAL;
}
+ if (amdgpu_sriov_vf(adev)) {
+ amdgpu_virt_init_setting(adev);
+ xgpu_nv_mailbox_set_irq_funcs(adev);
+ }
+
return 0;
}
static int nv_common_late_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ if (amdgpu_sriov_vf(adev))
+ xgpu_nv_mailbox_get_irq(adev);
+
return 0;
}
static int nv_common_sw_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ if (amdgpu_sriov_vf(adev))
+ xgpu_nv_mailbox_add_irq_id(adev);
+
return 0;
}
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