Merge branch 'drm-next-4.14' of git://people.freedesktop.org/~agd5f/linux into drm-next

More changes for 4.14.  Highlights:
- command submission overhead improvements
- Huge page support for vega10
- physical mode support for mjpeg for asics that don't support UVD vm
- improve ttm_mem_type_manager_func debug
- misc ttm fixes, cleanups
- misc gpuvm cleanups

* 'drm-next-4.14' of git://people.freedesktop.org/~agd5f/linux: (26 commits)
  drm/ttm: use reservation_object_trylock in ttm_bo_individualize_resv v2
  drm/amdgpu: fix vega10 graphic hang issue in S3 test
  drm/amdgpu: bump version for support of UVD MJPEG decode
  drm/amdgpu: add MJPEG check for UVD physical mode msg buffer
  drm/ttm: Fix accounting error when fail to get pages for pool
  drm/amd/amdgpu: expose fragment size as module parameter (v2)
  drm/amd/amdgpu: store fragment_size in vm_manager
  drm/amdgpu: rename VM invalidated to moved
  drm/amdgpu: separate bo_va structure
  drm/amdgpu: drop the extra VM huge page flag v2
  drm/amdgpu: remove superflous amdgpu_bo_kmap in the VM
  drm/amdgpu: cleanup static CSA handling
  drm/amdgpu: SHADOW and VRAM_CONTIGUOUS flags shouldn't be used by userspace
  drm/amdgpu: save list length when fence is signaled
  drm/amdgpu: move vram usage tracking into the vram manager v2
  drm/amdgpu: move gtt usage tracking into the gtt manager v2
  drm/amdgpu: move debug print into the MM managers
  drm/amdgpu: fix incorrect use of the lru_lock
  drm/radeon: fix incorrect use of the lru_lock
  drm/ttm: make ttm_mem_type_manager_func debug more useful
  ...

1 files changed, 4 insertions, 3 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 408723ef157c..4f2788b61a08 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -124,7 +124,7 @@ static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
 
 static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
 {
-	uint32_t tmp;
+	uint32_t tmp, field;
 
 	/* Setup L2 cache */
 	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
@@ -143,9 +143,10 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 	WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);
 
+	field = adev->vm_manager.fragment_size;
 	tmp = mmVM_L2_CNTL3_DEFAULT;
-	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
-	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 	WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);
 
 	tmp = mmVM_L2_CNTL4_DEFAULT;