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authorRex Zhu <Rex.Zhu@amd.com>2016-11-04 20:35:46 +0800
committerAlex Deucher <alexander.deucher@amd.com>2016-11-11 10:21:04 -0500
commitaa4747c00a2dd034c5fdf70ca73b1674ca15beb3 (patch)
tree9e3cc3ab768fc3c1955c5090a06ac2fd26208564 /drivers/gpu/drm/amd/amdgpu/ci_dpm.c
parentdc2f8a9aa98c5983d5faacf7e9843f8d15b5da9c (diff)
downloadtalos-op-linux-aa4747c00a2dd034c5fdf70ca73b1674ca15beb3.tar.gz
talos-op-linux-aa4747c00a2dd034c5fdf70ca73b1674ca15beb3.zip
drm/amdgpu: refine uvd_4.2 clock gate sequence.
1. partial revert commit 91db308d6e96. not set uvd bypass mode. 2. enable uvd cg before initialize uvd. 3. set uvd clock to default value 100MHz. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/ci_dpm.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/ci_dpm.c8
1 files changed, 0 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index bd690a21fdfa..fe42e2fb2622 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -4202,11 +4202,6 @@ static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
if (!gate) {
/* turn the clocks on when decoding */
- ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
- AMD_CG_STATE_UNGATE);
- if (ret)
- return ret;
-
if (pi->caps_uvd_dpm ||
(adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
pi->smc_state_table.UvdBootLevel = 0;
@@ -4223,9 +4218,6 @@ static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
ret = ci_enable_uvd_dpm(adev, false);
if (ret)
return ret;
-
- ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
- AMD_CG_STATE_GATE);
}
return ret;
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