diff options
author | Chen-Yu Tsai <wens@csie.org> | 2015-08-11 13:32:56 +0800 |
---|---|---|
committer | Herbert Xu <herbert@gondor.apana.org.au> | 2015-08-13 15:13:23 +0800 |
commit | 7ab64628bb4ab139aea9f1238ce6f945be580773 (patch) | |
tree | e7cc8e5098409c68bfa79d2f27d3b91524fffcab /drivers/crypto/sunxi-ss/sun4i-ss-core.c | |
parent | ca6bc691b1b7cf45862410952806f73c1aa62fe6 (diff) | |
download | talos-op-linux-7ab64628bb4ab139aea9f1238ce6f945be580773.tar.gz talos-op-linux-7ab64628bb4ab139aea9f1238ce6f945be580773.zip |
crypto: sunxi-ss - Add optional reset control support
On sun6i and later platforms, the reset control is split out of the
clock gates. Add support for an optional reset control.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/sunxi-ss/sun4i-ss-core.c')
-rw-r--r-- | drivers/crypto/sunxi-ss/sun4i-ss-core.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-core.c b/drivers/crypto/sunxi-ss/sun4i-ss-core.c index 0b79b58c913b..eab6fe227fa0 100644 --- a/drivers/crypto/sunxi-ss/sun4i-ss-core.c +++ b/drivers/crypto/sunxi-ss/sun4i-ss-core.c @@ -22,6 +22,7 @@ #include <linux/scatterlist.h> #include <linux/interrupt.h> #include <linux/delay.h> +#include <linux/reset.h> #include "sun4i-ss.h" @@ -253,6 +254,14 @@ static int sun4i_ss_probe(struct platform_device *pdev) } dev_dbg(&pdev->dev, "clock ahb_ss acquired\n"); + ss->reset = devm_reset_control_get_optional(&pdev->dev, "ahb"); + if (IS_ERR(ss->reset)) { + if (PTR_ERR(ss->reset) == -EPROBE_DEFER) + return PTR_ERR(ss->reset); + dev_info(&pdev->dev, "no reset control found\n"); + ss->reset = NULL; + } + /* Enable both clocks */ err = clk_prepare_enable(ss->busclk); if (err != 0) { @@ -275,6 +284,15 @@ static int sun4i_ss_probe(struct platform_device *pdev) goto error_clk; } + /* Deassert reset if we have a reset control */ + if (ss->reset) { + err = reset_control_deassert(ss->reset); + if (err) { + dev_err(&pdev->dev, "Cannot deassert reset control\n"); + goto error_clk; + } + } + /* * The only impact on clocks below requirement are bad performance, * so do not print "errors" @@ -352,6 +370,8 @@ error_alg: break; } } + if (ss->reset) + reset_control_assert(ss->reset); error_clk: clk_disable_unprepare(ss->ssclk); error_ssclk: @@ -376,6 +396,8 @@ static int sun4i_ss_remove(struct platform_device *pdev) } writel(0, ss->base + SS_CTL); + if (ss->reset) + reset_control_assert(ss->reset); clk_disable_unprepare(ss->busclk); clk_disable_unprepare(ss->ssclk); return 0; |