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authorChen-Yu Tsai <wens@csie.org>2017-05-22 14:25:48 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-06-07 15:32:16 +0200
commitf2fe1b640f8d5c3567ea1088544bf55e4d9654d8 (patch)
tree5fd250bdd847ce47cf21e0bbf41d6562af57c4c7 /drivers/clk
parentfaea8b0e33c2e6a276d34a755258bb2176553616 (diff)
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clk: sunxi-ng: a83t: Fix audio PLL divider offset
The divider of the audio PLL has an offset of 1. Fix this in the driver. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-a83t.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
index a9c5cc87d9d0..947f9f6e05d2 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
@@ -80,7 +80,7 @@ static struct ccu_nm pll_audio_clk = {
.enable = BIT(31),
.lock = BIT(2),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
- .m = _SUNXI_CCU_DIV_OFFSET(0, 6, 0),
+ .m = _SUNXI_CCU_DIV(0, 6),
.common = {
.reg = SUN8I_A83T_PLL_AUDIO_REG,
.lock_reg = CCU_SUN8I_A83T_LOCK_REG,
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