diff options
| author | Heiko Stübner <heiko@sntech.de> | 2016-07-29 15:56:55 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2016-08-08 10:57:21 +0200 |
| commit | e6cebc7273d54259362c7e44a4134d829f38ac59 (patch) | |
| tree | 2aa4f6521f4ac5d84a2406c570dea858fc05bdec /drivers/clk/rockchip/clk-pll.c | |
| parent | 4f4e0491670a2bc41887dc2c06782fa39e665d5c (diff) | |
| download | talos-op-linux-e6cebc7273d54259362c7e44a4134d829f38ac59.tar.gz talos-op-linux-e6cebc7273d54259362c7e44a4134d829f38ac59.zip | |
clk: rockchip: use general clock flag when registering pll
Add the general flags the pll list already contains to the clock init,
so that needed clock flags can be used for plls.
Signed-off-by: Heiko Stübner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk-pll.c')
| -rw-r--r-- | drivers/clk/rockchip/clk-pll.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index db81e454166b..9c1373e81683 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -837,7 +837,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, u8 num_parents, int con_offset, int grf_lock_offset, int lock_shift, int mode_offset, int mode_shift, struct rockchip_pll_rate_table *rate_table, - u8 clk_pll_flags) + unsigned long flags, u8 clk_pll_flags) { const char *pll_parents[3]; struct clk_init_data init; @@ -892,7 +892,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, init.name = pll_name; /* keep all plls untouched for now */ - init.flags = CLK_IGNORE_UNUSED; + init.flags = flags | CLK_IGNORE_UNUSED; init.parent_names = &parent_names[0]; init.num_parents = 1; |
