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| author | Andrew Jeffery <andrew@aj.id.au> | 2019-10-10 12:37:25 +1030 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-11-08 08:48:41 -0800 |
| commit | 3696eebd810cf084b3662d3c3b85cd84b61090f3 (patch) | |
| tree | c948172d8bd4687a297837c14d97c04edbd13759 /drivers/clk/mediatek/clk-mt2712.c | |
| parent | 309d673e9596f9706e72615583f2f689cf3fbfb5 (diff) | |
| download | talos-op-linux-3696eebd810cf084b3662d3c3b85cd84b61090f3.tar.gz talos-op-linux-3696eebd810cf084b3662d3c3b85cd84b61090f3.zip | |
clk: ast2600: Add RMII RCLK gates for all four MACs
RCLK is a fixed 50MHz clock derived from HPLL/HCLK that is described by a
single gate for each MAC.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lkml.kernel.org/r/20191010020725.3990-3-andrew@aj.id.au
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mt2712.c')
0 files changed, 0 insertions, 0 deletions
