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authorManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2018-03-26 23:08:59 +0530
committerStephen Boyd <sboyd@kernel.org>2018-04-06 14:17:46 -0700
commita83387729af8a7ded74e7155efb9468cefe081bd (patch)
treef7b6e300fceffe88965cbe3501f07b4d58a342ea /drivers/clk/actions/owl-mux.c
parent103c5e1b1026e4b3b025bbec9f4c586708269f3e (diff)
downloadtalos-op-linux-a83387729af8a7ded74e7155efb9468cefe081bd.tar.gz
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clk: actions: Add mux clock support
Add support for Actions Semi mux clock together with helper functions to be used in composite clock. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/actions/owl-mux.c')
-rw-r--r--drivers/clk/actions/owl-mux.c60
1 files changed, 60 insertions, 0 deletions
diff --git a/drivers/clk/actions/owl-mux.c b/drivers/clk/actions/owl-mux.c
new file mode 100644
index 000000000000..f9c6cf2540e4
--- /dev/null
+++ b/drivers/clk/actions/owl-mux.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL mux clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+
+#include "owl-mux.h"
+
+u8 owl_mux_helper_get_parent(const struct owl_clk_common *common,
+ const struct owl_mux_hw *mux_hw)
+{
+ u32 reg;
+ u8 parent;
+
+ regmap_read(common->regmap, mux_hw->reg, &reg);
+ parent = reg >> mux_hw->shift;
+ parent &= BIT(mux_hw->width) - 1;
+
+ return parent;
+}
+
+static u8 owl_mux_get_parent(struct clk_hw *hw)
+{
+ struct owl_mux *mux = hw_to_owl_mux(hw);
+
+ return owl_mux_helper_get_parent(&mux->common, &mux->mux_hw);
+}
+
+int owl_mux_helper_set_parent(const struct owl_clk_common *common,
+ struct owl_mux_hw *mux_hw, u8 index)
+{
+ u32 reg;
+
+ regmap_read(common->regmap, mux_hw->reg, &reg);
+ reg &= ~GENMASK(mux_hw->width + mux_hw->shift - 1, mux_hw->shift);
+ regmap_write(common->regmap, mux_hw->reg,
+ reg | (index << mux_hw->shift));
+
+ return 0;
+}
+
+static int owl_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct owl_mux *mux = hw_to_owl_mux(hw);
+
+ return owl_mux_helper_set_parent(&mux->common, &mux->mux_hw, index);
+}
+
+const struct clk_ops owl_mux_ops = {
+ .get_parent = owl_mux_get_parent,
+ .set_parent = owl_mux_set_parent,
+ .determine_rate = __clk_mux_determine_rate,
+};
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