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author | Linus Torvalds <torvalds@linux-foundation.org> | 2018-06-14 16:25:43 +0900 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2018-06-14 16:25:43 +0900 |
commit | 4b4bb99b6246007eccbc0731eae0b6742c24efa5 (patch) | |
tree | c81d34499eb1e89101741395ef345be43d6a7c71 /drivers/acpi/acpi_lpss.c | |
parent | 9bca19a01d50143b736f0f59eb3ccc05b1106172 (diff) | |
parent | 414c52b7899aa9097c2fa8444654a866e1df4a0c (diff) | |
download | talos-op-linux-4b4bb99b6246007eccbc0731eae0b6742c24efa5.tar.gz talos-op-linux-4b4bb99b6246007eccbc0731eae0b6742c24efa5.zip |
Merge tag 'pwm/for-4.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm
Pull pwm updates from Thierry Reding:
"This contains a couple of fixes and cleanups for the Meson and
ACPI/LPSS drivers as well as capture support for STM32.
Note that given the cross- subsystem changes, the STM32 patches were
merged through the MFD and PWM trees, both sharing an immutable
branch"
* tag 'pwm/for-4.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm:
pwm: stm32: Fix build warning with CONFIG_DMA_ENGINE disabled
pwm: stm32: Enforce dependency on CONFIG_MFD_STM32_TIMERS
ACPI / LPSS: Add missing prv_offset setting for byt/cht PWM devices
pwm: lpss: platform: Save/restore the ctrl register over a suspend/resume
dt-bindings: mfd: stm32-timers: Add support for dmas
pwm: simplify getting .drvdata
pwm: meson: Fix allocation of PWM channel array
Diffstat (limited to 'drivers/acpi/acpi_lpss.c')
-rw-r--r-- | drivers/acpi/acpi_lpss.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c index cb6ac5c65c2e..38a286975c31 100644 --- a/drivers/acpi/acpi_lpss.c +++ b/drivers/acpi/acpi_lpss.c @@ -233,11 +233,13 @@ static const struct lpss_device_desc lpt_sdio_dev_desc = { static const struct lpss_device_desc byt_pwm_dev_desc = { .flags = LPSS_SAVE_CTX, + .prv_offset = 0x800, .setup = byt_pwm_setup, }; static const struct lpss_device_desc bsw_pwm_dev_desc = { .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, + .prv_offset = 0x800, .setup = bsw_pwm_setup, }; |