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| author | Len Brown <len.brown@intel.com> | 2013-11-09 00:30:16 -0500 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2013-11-12 23:16:02 +0100 |
| commit | 144b44b1355df48eac7fee4c7519f4be0aafa4a3 (patch) | |
| tree | 8d2d1d0c18acb9bc328898b4f3b1c61fede8be7e /arch/x86 | |
| parent | 5e01dc7b26d9f24f39abace5da98ccbd6a5ceb52 (diff) | |
| download | talos-op-linux-144b44b1355df48eac7fee4c7519f4be0aafa4a3.tar.gz talos-op-linux-144b44b1355df48eac7fee4c7519f4be0aafa4a3.zip | |
tools / power turbostat: Support Silvermont
Support the next generation Intel Atom processor
mirco-architecture, formerly called Silvermont.
The server version, formerly called "Avoton",
is named the "Intel(R) Atom(TM) Processor C2000 Product Family".
The client version, formerly called "Bay Trail",
is named the "Intel Atom Processor Z3000 Series",
as well as various "Intel Pentium Processor"
and "Intel Celeron Processor" brands, depending
on form-factor.
Silvermont has a set of MSRs not far off from NHM,
but the RAPL register set is a sub-set of those previously supported.
Signed-off-by: Len Brown <len.brown@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/include/uapi/asm/msr-index.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h index bb0465090ae5..940ed3fd889a 100644 --- a/arch/x86/include/uapi/asm/msr-index.h +++ b/arch/x86/include/uapi/asm/msr-index.h @@ -147,6 +147,8 @@ #define MSR_PP1_ENERGY_STATUS 0x00000641 #define MSR_PP1_POLICY 0x00000642 +#define MSR_CORE_C1_RES 0x00000660 + #define MSR_AMD64_MC0_MASK 0xc0010044 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) |
