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| author | =?UTF-8?q?Christian=20K=C3=B6nig?= <ckoenig.leichtzumerken@gmail.com> | 2018-01-11 14:23:29 +0100 |
|---|---|---|
| committer | Bjorn Helgaas <helgaas@kernel.org> | 2018-01-11 11:22:39 -0600 |
| commit | f32ab7547161b9fa7ebfbc4f18ea1eb3fd49fe25 (patch) | |
| tree | f806a04056ffadf4bdc92e4d70e1ff1488c713b0 /arch/x86/include/asm/pci_x86.h | |
| parent | 1291a0d5049dbc06baaaf66a9ff3f53db493b19b (diff) | |
| download | talos-op-linux-f32ab7547161b9fa7ebfbc4f18ea1eb3fd49fe25.tar.gz talos-op-linux-f32ab7547161b9fa7ebfbc4f18ea1eb3fd49fe25.zip | |
x86/PCI: Add "pci=big_root_window" option for AMD 64-bit windows
Only try to enable a 64-bit window on AMD CPUs when "pci=big_root_window"
is specified.
This taints the kernel because the new 64-bit window uses address space we
don't know anything about, and it may contain unreported devices or memory
that would conflict with the window.
The pci_amd_enable_64bit_bar() quirk that enables the window is specific to
AMD CPUs. The generic solution would be to have the firmware enable the
window and describe it in the host bridge's _CRS method, or at least
describe it in the _PRS method so the OS would have the option of enabling
it.
Signed-off-by: Christian König <christian.koenig@amd.com>
[bhelgaas: changelog, extend doc, mention taint in dmesg]
Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
Diffstat (limited to 'arch/x86/include/asm/pci_x86.h')
| -rw-r--r-- | arch/x86/include/asm/pci_x86.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index 7a5d6695abd3..eb66fa9cd0fc 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h @@ -38,6 +38,7 @@ do { \ #define PCI_NOASSIGN_ROMS 0x80000 #define PCI_ROOT_NO_CRS 0x100000 #define PCI_NOASSIGN_BARS 0x200000 +#define PCI_BIG_ROOT_WINDOW 0x400000 extern unsigned int pci_probe; extern unsigned long pirq_table_addr; |
