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| author | Paul Walmsley <paul.walmsley@sifive.com> | 2019-11-22 18:59:09 -0800 |
|---|---|---|
| committer | Paul Walmsley <paul.walmsley@sifive.com> | 2019-11-22 18:59:09 -0800 |
| commit | 5ba9aa56e6d3e8fddb954c2f818d1ce0525235bb (patch) | |
| tree | b9f61d0544ed06b7f07000a11797711cdd97d83f /arch/riscv/lib/uaccess.S | |
| parent | 4a979862dde46b738316014ca4995eae2f428413 (diff) | |
| parent | 405fe7aa0dbaa6cb8cfe62771eee67076d30aca1 (diff) | |
| download | talos-op-linux-5ba9aa56e6d3e8fddb954c2f818d1ce0525235bb.tar.gz talos-op-linux-5ba9aa56e6d3e8fddb954c2f818d1ce0525235bb.zip | |
Merge branch 'next/nommu' into for-next
Conflicts:
arch/riscv/boot/Makefile
arch/riscv/include/asm/sbi.h
Diffstat (limited to 'arch/riscv/lib/uaccess.S')
| -rw-r--r-- | arch/riscv/lib/uaccess.S | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S index ed2696c0143d..fecd65657a6f 100644 --- a/arch/riscv/lib/uaccess.S +++ b/arch/riscv/lib/uaccess.S @@ -18,7 +18,7 @@ ENTRY(__asm_copy_from_user) /* Enable access to user memory */ li t6, SR_SUM - csrs CSR_SSTATUS, t6 + csrs CSR_STATUS, t6 add a3, a1, a2 /* Use word-oriented copy only if low-order bits match */ @@ -47,7 +47,7 @@ ENTRY(__asm_copy_from_user) 3: /* Disable access to user memory */ - csrc CSR_SSTATUS, t6 + csrc CSR_STATUS, t6 li a0, 0 ret 4: /* Edge case: unalignment */ @@ -72,7 +72,7 @@ ENTRY(__clear_user) /* Enable access to user memory */ li t6, SR_SUM - csrs CSR_SSTATUS, t6 + csrs CSR_STATUS, t6 add a3, a0, a1 addi t0, a0, SZREG-1 @@ -94,7 +94,7 @@ ENTRY(__clear_user) 3: /* Disable access to user memory */ - csrc CSR_SSTATUS, t6 + csrc CSR_STATUS, t6 li a0, 0 ret 4: /* Edge case: unalignment */ @@ -114,11 +114,11 @@ ENDPROC(__clear_user) /* Fixup code for __copy_user(10) and __clear_user(11) */ 10: /* Disable access to user memory */ - csrs CSR_SSTATUS, t6 + csrs CSR_STATUS, t6 mv a0, a2 ret 11: - csrs CSR_SSTATUS, t6 + csrs CSR_STATUS, t6 mv a0, a1 ret .previous |
