diff options
| author | Olof Johansson <olof@lixom.net> | 2007-10-16 00:58:59 +1000 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2007-10-17 22:30:09 +1000 |
| commit | f66bce5e6aa1388289c04496c3fcae7bebf5f905 (patch) | |
| tree | 7e788739a51947f1caff47f9b5226cad739e3805 /arch/powerpc/mm/hash_utils_64.c | |
| parent | 8129535b6bcf40be62af2ae6b9234494f39725dd (diff) | |
| download | talos-op-linux-f66bce5e6aa1388289c04496c3fcae7bebf5f905.tar.gz talos-op-linux-f66bce5e6aa1388289c04496c3fcae7bebf5f905.zip | |
[POWERPC] Add 1TB workaround for PA6T
PA6T has a bug where the slbie instruction does not honor the large
segment bit. As a result, we have to always use slbia when switching
context.
We don't have to worry about changing the slbie's during fault processing,
since they should never be replacing one VSID with another using the
same ESID. I.e. there's no risk for inserting duplicate entries due to a
failed slbie of the old entry. So as long as we clear it out on context
switch we should be fine.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/mm/hash_utils_64.c')
| -rw-r--r-- | arch/powerpc/mm/hash_utils_64.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c index 09da90b53850..c78dc912411f 100644 --- a/arch/powerpc/mm/hash_utils_64.c +++ b/arch/powerpc/mm/hash_utils_64.c @@ -212,6 +212,7 @@ static int __init htab_dt_scan_seg_sizes(unsigned long node, return 1; } } + cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B; return 0; } |
